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Freescale Semiconductor DSP56366 User Manual

24-bit digital signal processor
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DSP56366 24-Bit Digital Signal
Processor
User Manual
Document Number: DSP56366UM
Rev. 4
08/2006

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Summary of Contents for Freescale Semiconductor DSP56366

  • Page 1 DSP56366 24-Bit Digital Signal Processor User Manual Document Number: DSP56366UM Rev. 4 08/2006...
  • Page 2 “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components...

  • Page 3: Table Of Contents

    DSP56366 Audio Processor Architecture ........
  • Page 4 HDI08 – DSP-Side Programmer’s Model ......... 6-5 TOC-2 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Freescale Semiconductor...
  • Page 5 ICR Double Host Request (HDRQ) Bit 2 ........6-21 Freescale Semiconductor DSP56366 24-Bit Digital Signal Processor, Rev. 4 TOC-3...
  • Page 6 SHI Individual Reset ..........7-11 TOC-4 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Freescale Semiconductor...
  • Page 7 C Master Mode ........7-24 DSP56366 24-Bit Digital Signal Processor, Rev. 4...
  • Page 8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21 ..... 8-24 8.3.3.9 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22 ....8-25 TOC-6 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Freescale Semiconductor...
  • Page 9 ESAI Transmit Shift Registers ..........8-40 8.3.10 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0) ....8-40 Freescale Semiconductor DSP56366 24-Bit Digital Signal Processor, Rev. 4 TOC-7...
  • Page 10 RCCR_1 Rx High Freq. Clock Polarity (RHCKP) - Bit 20 ..... 9-9 TOC-8 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Freescale Semiconductor...
  • Page 11 DAX Audio Data Register Empty (XADE)—Bit 0 ......10-8 Freescale Semiconductor DSP56366 24-Bit Digital Signal Processor, Rev. 4 TOC-9...
  • Page 12 TCSR Timer Overflow Flag (TOF) Bit 20 ....... . 11-11 TOC-10 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Freescale Semiconductor...
  • Page 13 DSP56366 Bootstrap Program ........
  • Page 14 Programming Sheets ............B-15 TOC-12 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Freescale Semiconductor...
  • Page 15 DSP56366 Block Diagram ........
  • Page 16 C Bus ........7-18 DSP56366 24-Bit Digital Signal Processor, Rev. 4...
  • Page 17 ESAI Common Control Register ......... D-34 Freescale Semiconductor DSP56366 24-Bit Digital Signal Processor, Rev. 4 LOF-3...
  • Page 18 GPIO Port E ............D-51 LOF-4 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Freescale Semiconductor...
  • Page 19 DSP56366 BSR Bit Definition ........
  • Page 20 DSP56366 Interrupt Vectors ........

  • Page 21: Freescale Semiconductor

    This manual describes the DSP56366 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56366 is a member of the DSP56300 family of programmable CMOS DSPs. Changes in core functionality specific to the DSP56366 are also described in this manual.

  • Page 22: Manual Conventions

    • Provides the BSDL listing for the DSP56366. APPENDIX D—PROGRAMMING REFERENCE • Lists peripheral addresses, interrupt addresses, and interrupt priorities for the DSP56366. Contains programming sheets listing the contents of the major DSP56366 registers for programmer reference. Manual Conventions The following conventions are used in this manual: •...

  • Page 23: Freescale Semiconductor

    — the reset instruction, written as “RESET,” — the reset operating state, written as “Reset,” and — the reset function, written as “reset.” DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor High True/Low True Signal Conventions Logic State...
  • Page 24 NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 25: Freescale Semiconductor

    This manual describes the DSP56366 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56366 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56366 is targeted to applications that require digital audio compression/decompression, sound field processing, acoustic equalization and other digital audio algorithms.

  • Page 26: Dsp56300 Core Description

    DSP56300 Core Description DSP56300 Core Description The DSP56366 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performance of Freescale's popular DSP56000 core family while retaining code compatibility with it. The DSP56300 core family offers a new level of performance in speed and power, provided by its rich instruction set and low power dissipation, thus enabling a new generation of wireless, telecommunications, and multimedia products.

  • Page 27: Freescale Semiconductor

    • 144-pin plastic TQFP package. DSP56366 Audio Processor Architecture This section defines the DSP56366 audio processor architecture. The audio processor is composed of the following units: • The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller, Instruction-Cache Controller, DMA Controller, PLL-based clock oscillator, Memory Module Interface, Peripheral Module Interface and the On-Chip Emulator (OnCE).

  • Page 28: Data Alu

    OnCE module • JTAG TAP • Memory In addition, the DSP56366 provides a set of on-chip peripherals, described in Overview". 1.4.1 Data ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core.

  • Page 29: Freescale Semiconductor

    • Position independent code support • Addressing modes optimized for DSP applications (including immediate offsets) • On-chip instruction cache controller • On-chip memory-expandable hardware stack DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor DSP56300 Core Functional Blocks...

  • Page 30: Internal Buses

    Direct Memory Access (DMA) The DMA block has the following features: • Six DMA channels supporting internal and external accesses • One-, two-, and three-dimensional transfers (including circular buffering) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Figure 1-1. Freescale Semiconductor...

  • Page 31: Freescale Semiconductor

    X data memory space, and Y data memory space. The data memory space is divided into X and Y data memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor : i = 0 to 7) to reduce clock noise .

  • Page 32: Off-Chip Memory Expansion

    • Eighteen external address lines Peripheral Overview The DSP56366 is designed to perform a wide variety of fixed-point digital signal processing functions. In addition to the core features previously discussed, the DSP56366 provides the following peripherals: • 8-bit parallel host interface (HDI08, with DMA support) to external hosts •...

  • Page 33: Host Interface (Hdi08)

    TIO0 is used as output the timer is functioning as either a timer, a watchdog or a Pulse Width Modulator. When the TIO0 pin is not used by the timer it can be used as a General Purpose Input/Output Pin. Refer Section 11, "Timer/ Event Counter". DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Peripheral Overview...

  • Page 34: Enhanced Serial Audio Interface (Esai)

    Digital Audio Transmitter (DAX) The DAX is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and IEC958 formats. For more information on the DAX, refer to DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 1-10 (ESAI_1)".

  • Page 35: Signal/Connection Descriptions

    Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals. Port D signals are the GPIO port signals which are multiplexed with the DAX signals. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor 2-1.

  • Page 36: Figure 2-1 Signals Identified By Functional Group

    SPDIF TRANSMITTER (DAX) ADO [PD1] ACI [PD0] TIMER 0 TIO0 [TIO0] Figure 2-1 Signals Identified by Functional Group DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 OnCE‰ ON-CHIP EMULATION/ DSP56366 PARALLEL HOST PORT (HDI08) Port B SERIAL AUDIO INTERFACE (ESAI)

  • Page 37: Power

    Quiet Ground — GND be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GND DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 2-2 Power Inputs...

  • Page 38: Clock And Pll

    Input PINIT/NMI Input Input DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Table 2-3 Grounds (continued) Description is an isolated ground for sections of the address bus I/O drivers. This is an isolated ground for sections of the data bus I/O drivers. This is an isolated ground for the bus control I/O drivers.

  • Page 39: External Memory Expansion Port (Port A)

    Output Tri-stated Output Tri-stated DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 2-5 External Address Bus Signals Address Bus — When the DSP is the bus master, A0 – A17 are active-high outputs that specify the address for external program and data memory accesses.
  • Page 40 Output Output (deasserted) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Signal Description Write Enable — When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0-D23).

  • Page 41: Interrupt And Mode Control

    The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Bus Grant —...

  • Page 42: Table 2-8 Interrupt And Mode Control

    Input RESET Input Input DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Table 2-8 Interrupt and Mode Control Signal Description Mode Select A/External Interrupt Request A — MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA...

  • Page 43: Parallel Host Interface (Hdi08)

    Input disconnected Input Input, output, or disconnected DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 2-9 Host Interface Reset Host Data — When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, these signals are lines 0 – 7 of the bidirectional, tri-state data bus.
  • Page 44 HWR/ Input PB12 Input, output, or disconnected DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 2-10 Table 2-9 Host Interface (continued) Reset GPIO Host Address Input 2 — When the HDI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus.
  • Page 45 HTRQ/ Output HTRQ PB14 Input, output, or disconnected DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 2-9 Host Interface (continued) Reset GPIO Host Chip Select — When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input.

  • Page 46: Serial Host Interface

    Signal Type Name Reset Input or output Tri-stated Input or output DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 2-12 Table 2-9 Host Interface (continued) Reset GPIO Host Acknowledge — When HDI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input.
  • Page 47 MOSI Input or output Tri-stated Input DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Signal Description SPI Master-In-Slave-Out — When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data.
  • Page 48 Input HREQ Input or Output Tri-stated DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 2-14 Signal Description SPI Slave Select — This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer.

  • Page 49: Enhanced Serial Audio Interface

    Input or output Input, output, or disconnected Input or output Input, output, or disconnected DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor State during Reset GPIO High Frequency Clock for Receiver — When programmed as an disconnected input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock.
  • Page 50 Input or output Input, output, or disconnected SCKT Input or output Input, output, or disconnected DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 2-16 State during Reset GPIO Frame Sync for Transmitter — This is the transmitter frame sync disconnected input/output signal.
  • Page 51 SDO3_1 SDI2/ Input SDI2_1 PC8/PE8 Input, output, or disconnected DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor State during Reset GPIO Serial Data Output 5 — When programmed as a transmitter, SDO5 is disconnected used to transmit data from the TX5 serial transmit shift register.
  • Page 52 SDO0/ Output SDO0_1 PC11/ Input, output, or PE11 disconnected DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 2-18 State during Reset GPIO Serial Data Output 2 — When programmed as a transmitter, SDO2 is disconnected used to transmit data from the TX2 serial transmit shift register When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 2.

  • Page 53: Enhanced Serial Audio Interface_1

    FST_1 Input or output disconnected Input, output, or disconnected DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Reset GPIO Frame Sync for Receiver_1 — This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers.
  • Page 54 SDI0_1 Input Input, output, or disconnected DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 2-20 Reset GPIO Receiver Serial Clock_1 — SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1).

  • Page 55: Spdif Transmitter Digital Audio Interface

    Output Disconnected Input, output, or disconnected DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Reset GPIO Serial Data Output 4_1 — When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register.

  • Page 56: Timer

    Input Input Output Tri-stated Input Input DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 2-22 Table 2-14 Timer Signal Reset Input Timer 0 Schmitt-Trigger Input/Output — When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input.

  • Page 57: Memory Configuration

    Data and Program Memory Maps The on-chip memory configuration of the DSP56366 is affected by the state of the CE (Cache Enable), MSW0, MSW1, and MS (Memory Switch) control bits in the OMR register, and by the SC bit in the Status Register.

  • Page 58: Table 3-2 On-Chip Ram Memory Locations

    Data and Program Memory Maps Bit Settings MSW1 MSW0 Bit Settings MSW1 MSW0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Table 3-2 On-chip RAM Memory Locations RAM Memory Locations Prog. $0000 - $0BFF $0000 - $07FF $0000 -$27FF...

  • Page 59: Figure 3-1 Memory Maps For Msw=(X,X), Ce=0, Ms=0, Sc=0

    BOOT ROM $FF0000 EXTERNAL $000800 2K INTERNAL $000000 1K I-CACHE ENABLED Figure 3-2 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor X DATA $FFFFFF INTERNAL I/O (128 words) $FFFF80 EXTERNAL...

  • Page 60: Figure 3-3 Memory Maps For Msw=(0,0), Ce=0 Ms=1, Sc=0

    EXTERNAL $002800 1K RAM $002400 INT. RESERVED $001C00 7K INTERNAL $000000 Figure 3-4 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 X DATA $FFFFFF INTERNAL I/O (128 words) $FFFF80 EXTERNAL $FFF000 INTERNAL...

  • Page 61: Figure 3-5 Memory Maps For Msw=(1,0), Ce=0, Ms=1, Sc=0

    BOOT ROM $FF0000 EXTERNAL $002400 9K INTERNAL $000000 1K I-CACHE ENABLED Figure 3-6 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor X DATA $FFFFFF INTERNAL I/O (128 words) $FFFF80 EXTERNAL...

  • Page 62: Figure 3-7 Memory Maps For Msw=(0,1), Ce=1, Ms=1, Sc=0

    EXTERNAL $002400 INT. RESERVED $001000 4K INTERNAL $000000 1K I-CACHE ENABLED Figure 3-8 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 X DATA $FFFFFF INTERNAL I/O (128 words) $FFFF80 EXTERNAL $FFF000 INTERNAL...

  • Page 63: Figure 3-10 Memory Maps For Msw=(X,X), Ce=1, Ms=0, Sc=1

    PROGRAM $FFFF EXTERNAL $0800 2K INTERNAL $0000 1K I-CACHE ENABLED Figure 3-10 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor X DATA $FFFF INTERNAL I/O (128 words) $FF80 EXTERNAL $C000...

  • Page 64: Figure 3-11 Memory Maps For Msw=(0,0), Ce=0, Ms=1, Sc=1

    $2800 1K RAM $2400 INT. RESERVED $1C00 7K INTERNAL $0000 Figure 3-12 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 X DATA $FFFF INTERNAL I/O (128 words) $FF80 EXTERNAL $C000 32K INTERNAL $4000 INT.

  • Page 65: Figure 3-13 Memory Maps For Msw=(1,0), Ce=0, Ms=1, Sc=1

    PROGRAM $FFFF EXTERNAL $2400 9K INTERNAL $0000 1K I-CACHE ENABLED Figure 3-14 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor X DATA $FFFF INTERNAL I/O (128 words) $FF80 EXTERNAL $C000...

  • Page 66: Figure 3-15 Memory Maps For Msw=(0,1), Ce=1, Ms=1, Sc=1

    EXTERNAL $2400 INT. RESERVED $1000 4K INTERNAL $0000 1K I-CACHE ENABLED Figure 3-16 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 3-10 X DATA $FFFF INTERNAL I/O (128 words) $FF80 EXTERNAL $C000...

  • Page 67: Dynamic Memory Configuration Switching

    Special attention should be given when running a memory switch routine using the OnCE™ port. Running the switch routine in Trace mode, for example, can cause the switch to complete after the MS bit change DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Contents".

  • Page 68: External Memory Support

    (after the switch), and thus might execute improperly. 3.1.5 External Memory Support The DSP56366 does not support the SSRAM memory type. It does support SRAM and DRAM as indicated in the DSP56300 24-Bit Digital Signal Processor Family Manual DSP56300FM.
  • Page 69 X:$FFFFCD X:$FFFFCC X:$FFFFCB X:$FFFFCA PORT B X:$FFFFC9 X:$FFFFC8 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Register Name DMA SOURCE ADDRESS REGISTER (DSR1) DMA DESTINATION ADDRESS REGISTER (DDR1) DMA COUNTER (DCO1) DMA CONTROL REGISTER (DCR1) DMA SOURCE ADDRESS REGISTER (DSR2)
  • Page 70 X:$FFFFC2 X:$FFFFC1 X:$FFFFC0 PORT C X:$FFFFBF X:$FFFFBE X:$FFFFBD DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 3-14 Register Name HOST TRANSMIT REGISTER (HOTX) HOST RECEIVE REGISTER (HORX) HOST BASE ADDRESS REGISTER (HBAR) HOST PORT CONTROL REGISTER (HPCR) HOST STATUS REGISTER (HSR)
  • Page 71 X:$FFFF9D X:$FFFF9C X:$FFFF9B X:$FFFF9A X:$FFFF99 X:$FFFF98 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Register Name ESAI RECEIVE SLOT MASK REGISTER B (RSMB) ESAI RECEIVE SLOT MASK REGISTER A (RSMA) ESAI TRANSMIT SLOT MASK REGISTER B (TSMB)
  • Page 72 X:$FFFF83 X:$FFFF82 X:$FFFF81 X:$FFFF80 ESAI MUX PIN Y:$FFFFAF CONTROL Y:$FFFFAE Y:$FFFFAD DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 3-16 Register Name Reserved Reserved Reserved SHI RECEIVE FIFO (HRX) SHI TRANSMIT REGISTER (HTX) SHI I C SLAVE ADDRESS REGISTER (HSAR)
  • Page 73 Y:$FFFFA9 Y:$FFFFA8 Y:$FFFFA7 Y:$FFFFA6 Y:$FFFFA5 Y:$FFFFA4 Y:$FFFFA3 Y:$FFFFA2 Y:$FFFFA1 Y:$FFFFA0 PORT E Y:$FFFF9F Y:$FFFF9E Y:$FFFF9D DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Register Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved...
  • Page 74 Y:$FFFF85 Y:$FFFF84 Y:$FFFF83 Y:$FFFF82 Y:$FFFF81 Y:$FFFF80 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 3-18 Register Name ESAI_1 RECEIVE SLOT MASK REGISTER B (RSMB_1) ESAI_1 RECEIVE SLOT MASK REGISTER A (RSMA_1) ESAI_1 TRANSMIT SLOT MASK REGISTER B (TSMB_1) ESAI_1 TRANSMIT SLOT MASK REGISTER A (TSMA_1)

  • Page 75: Operating Mode Register (Omr)

    Core Configuration Introduction This chapter contains DSP56300 core configuration information details specific to the DSP56366. These include the following: • Operating modes • Bootstrap program • Interrupt sources and priorities • DMA request sources • • PLL control register •...

  • Page 76: Asynchronous Bus Arbitration Enable (Abe) - Bit 13

    The Patch Enable function is activated by setting bit 23 (PEN) in the OMR Register. The PEN bit is cleared by hardware reset. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Table 4-1 Operating Mode Register (OMR) - Address Tracing Enable - Address Priority Disable - Asyn.
  • Page 77 ; replace ROM code by PATCH DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor 132,55,0,0,0 $100 $ffafec ; ROM area Start $ffafff ; ROM area End P:START #M_PROMS,r0...

  • Page 78: Table 4-2 Dsp56366 Operating Modes

    MODB, MODC and MODD pins during reset. Each operating mode is briefly described below. Except for modes 0 and 8, the operation of all other modes is defined by the Bootstrap ROM source code in A , "Bootstrap ROM Contents". Mode DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 #(PATCH_DATA_END-PATCH_DATA_START+1),PATCH_LOOP p:(r1)+,x0 x0,p:(r2)+ #M_PROMS...

  • Page 79: Table 4-3 Dsp56366 Mode Descriptions

    The program words will be stored in contiguous PRAM memory locations starting at the specified starting address. After reading the program words, program execution starts from the same address where loading started. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Reset...

  • Page 80: Interrupt Priority Registers

    As in Mode C, but HDI08 is set for interfacing to Freescale 68302 bus. Interrupt Priority Registers There are two interrupt priority registers in the DSP56366: 1. IPR-C is dedicated for DSP56300 Core interrupt sources. 2. IPR-P is dedicated for DSP56366 peripheral interrupt sources.

  • Page 81: Figure 4-1 Interrupt Priority Register P

    Reserved bit. Read as zero, should be written with zero for future compatibility. IDL2 IDL1 IDL0 ICL2 D5L1 D5L0 D4L1 D4L0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor DAL1 DAL0 HDL1 HDL0 SHL1 Figure 4-1 Interrupt Priority Register P ICL1...

  • Page 82: Table 4-5 Interrupt Sources Priorities Within An Ipl

    Table 4-5 Interrupt Sources Priorities Within an IPL Priority Level 3 (Nonmaskable) Highest Lowest Levels 0, 1, 2 (Maskable) Highest DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Interrupt Source Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap...
  • Page 83 ESAI_1 Receive Even Data ESAI_1 Receive Data ESAI_1 Receive Last Slot ESAI_1 Transmit Data with Exception Status ESAI_1 Transmit Last Slot ESAI_1 Transmit Even Data Lowest ESAI_1 Transmit Data DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 84: Table 4-6 Dsp56366 Interrupt Vectors

    0 - 2 VBA:$3E 0 - 2 VBA:$40 0 - 2 VBA:$42 0 - 2 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 4-10 Table 4-6 DSP56366 Interrupt Vectors Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap...
  • Page 85 VBA:$7E 0 - 2 VBA:$80 0 - 2 VBA:$FE 0 - 2 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor SHI Receive FIFO Not Empty Reserved SHI Receive FIFO Full SHI Receive Overrun Error SHI Bus Error...

  • Page 86: Table 4-7 Dma Request Sources

    01111 10000 10001 10010 10011 10100 10101 10110 10111-11111 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 4-12 Table 4-7. Table 4-7 DMA Request Sources Requesting Device External (IRQA pin) External (IRQB pin) External (IRQC pin) External (IRQD pin)

  • Page 87: Pll Multiplication Factor (Mf0-Mf11)

    The Crystal Range (XTLR) bit controls the on-chip crystal oscillator transconductance. The on-chip crystal oscillator is not used on the DSP56366 since no XTAL pin is available. The XTLR bit is set to zero during hardware reset in the DSP56366.

  • Page 88: Jtag Boundary Scan Register (Bsr)

    0000 JTAG Boundary Scan Register (BSR) The boundary scan register (BSR) in the DSP56366 JTAG implementation contains bits for all device signal and clock pins and associated control signals. All bidirectional pins have a single register bit in the boundary scan register for pin data, and are controlled by an associated control bit in the boundary scan register.
  • Page 89 Input/Output Input/Output Output3 Output3 Output3 A[17:9] — Output3 Output3 Output3 Output3 Output3 Output3 Output3 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor BSR Cell Pin Name Type Data HAD6 Data HAD6 Data HAD7 Data HAD7 Data HAS/A0...
  • Page 90 Input/Output Output2 Input PINIT Input SCKR_1 SCKR_1 Input/Output FSR_1 FSR_1 Input/Output RD,WR — DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 4-16 BSR Cell Pin Name Type Data 119 HSCKR Data 120 HSCKR Control 121 HSCKT Data 122 HSCKT...
  • Page 91 Pin Name Pin Type EXTAL Input SCKT_1 — SCKT_1 Input/Output — Output3 — Output3 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor BSR Cell Pin Name Type Data 145 SS Control 146 SCK/SCL Data 147 SCK/SCL Control...
  • Page 92 JTAG Boundary Scan Register (BSR) NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 4-18 Freescale Semiconductor...

  • Page 93: Introduction

    The GPIO functionality of Port D is controlled by three registers: Port D control register (PCRD), Port D direction register (PRRD) and Port D data register (PDRD). These registers are described in "Digital Audio Transmitter". DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor of this document. (ESAI)".

  • Page 94: Port E Signals And Registers

    The timer/event counter signal (TIO), when not used as a timer signal can be configured as a GPIO signal. The signal is controlled by the appropriate timer control status register (TCSR). The register is described Section 11, "Timer/ Event Counter". DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Section 9, "Enhanced Serial Audio Interface Freescale Semiconductor...

  • Page 95: Host Interface (Hdi08)

    — Memory-mapped registers allow the standard MOVE instruction to be used to transfer data between the DSP and the external host. — Special MOVEP instruction provides for I/O service capability using fast interrupts. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 96: Interface - Host Side

    – Host to DSP — Host Command • Handshaking Protocols: — Software polled — Interrupt-driven (Interrupts are compatible with most processors, including the MC68000, 8051, HC11 and Hitachi H8). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 97: Hdi08 Host Port Signals

    GPIO pins if they are not needed for their HDI08 function. Summary of the HDI08 signals. HDI08 Port Pin Multiplexed address/data bus Mode HAD0-HAD7 HAS/HA0 HA8/HA1 HA9/HA2 HCS/HA10 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Section 2, "Signal/Connection Table 6-1 HDI08 Signal Summary Non Multiplexed bus Mode HAD0-HAD7 HAS/HAS HA10 HDI08 Host Port Signals Descriptions".

  • Page 98: Hdi08 Block Diagram

    HOTX, HORX) can be accessed the DSP core. The bottom row of registers (ISR, ICR, CVR, IVR, RXH:RXM:RXL and TXH:TXM:TXL) can be accessed by the host processor. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Table 6-2 Strobe Signals Support signals...

  • Page 99: Hdi08 – Dsp-Side Programmer's Model

    DSP memory and the HDI08 registers or vice-versa. The HOTX and HORX registers may be serviced by the on-chip DMA controller for data transfers. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Core DMA Data Bus...

  • Page 100: Host Transmit Data Register (Hotx)

    DMA Channel may be programmed to write to HOTX when HTDE is set. To prevent the previous data from being overwritten, data should not be written to the HOTX until the HTDE flag is set. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 101: Hcr Host Transmit Interrupt Enable (Htie) Bit 1

    Host interrupt request priorities: If more than one interrupt request source is asserted and enabled (e.g. HRDF=1, HCP=1, HRIE=1 and HCIE=1), the HDI08 generates interrupt requests according to the following table: DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor NOTE DSP56300 Family Manual Section 6.5.9, "DSP-Side Registers After...

  • Page 102: Hcr Host Dma Mode Control Bits (Hdm0, Hdm1, Hdm2) Bits 5-7

    DMA operation disabled DMA Operation Enabled. Host may set HM1 or HM0 in the ICR to enable DMA transfers. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Table 6-4 HDI08 IRQ Interrupt Source Host Command (HCP=1) Transmit Data (HTDE=1)
  • Page 103 (RXL or TXL), the address counter is not incremented but is loaded with the value in HDM[1:0]. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion and eliminates the need DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor HDI08 –...

  • Page 104: Hsr Host Transmit Data Empty (Htde) Bit 1

    The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending. The HCP bit reflects the status of the HC bit in the command vector register (CVR). HC and HCP are cleared DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-10 Reset".

  • Page 105: Hsr Host Flags 0,1 (Hf0,Hf1) Bits 3-4

    6.5.5.1 HBAR Base Address (BA[10:3]) Bits 0-7 These bits define the base address where the host side registers are mapped into the bus address space. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor BA10 HDI08 – DSP-Side Programmer’s Model Figure 6-5.

  • Page 106: Hpcr Host Gpio Port Enable (Hgen) Bit 0

    If the HGEN bit is set, pins configured as GPIO are enabled. If this bit is cleared, pins configured as GPIO are disconnected: outputs are high impedance, inputs are electrically disconnected. Pins configured as HDI08 are not affected by the state of HGEN. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-12 Latch...

  • Page 107: Hpcr Host Address Line 8 Enable (Ha8En) Bit 1

    HDI08 pins are configured as GPIO pins according to the value of HDDR and HDR registers. 6.5.6.8 HPCR Reserved Bit 7 This bit is reserved. It reads as zero and should be written with zero for future compatibility. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor HDI08 – DSP-Side Programmer’s Model 6-13...

  • Page 108: Hpcr Host Address Strobe Polarity (Hasp) Bit 10

    In the single strobe bus mode, the HDS (Data-Strobe) signal qualifies the access, while the HRW (Read/Write) signal specifies the direction of the access. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-14 Figure 6-7 Single strobe bus...

  • Page 109: Hpcr Host Chip Select Polarity (Hcsp) Bit 13

    (GPIO)". If bit DRxx is set, the corresponding HDI08 pin is configured as an output signal. If bit DRxx is cleared, the corresponding HDI08 pin is configured as an input signal. See DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 110: Dsp-Side Registers After Reset

    RESET instruction. The individual reset (IR) is caused by clearing the HEN bit (HPCR bit 6). The stop reset (ST) is caused by executing the STOP instruction. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-16 Table 6-6 HDR and HDDR Functionality Read only bit.

  • Page 111: Host Interface Dsp Core Interrupts

    HDI08 register (clearing HRDF or HTDE, for example) to clear the interrupt. In the case of host command interrupts, the interrupt acknowledge from the DSP core program controller clears the pending interrupt condition. Figure 6-11 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 6-7 DSP-Side Registers after Reset Reset Reset —...

  • Page 112: Hdi08 – External Host Programmer's Model

    DSP as a fast device, and data can be transferred between the host processor and the DSP at the fastest host processor data rate. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-18...

  • Page 113: Interface Control Register (Icr)

    Bits 2, 5 and 6 of the ICR are affected by the condition of HDM[2:0] (HCR bits 5-7), as shown in Figure 6-12. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 6-8 HDI08 Host Side Register Map...

  • Page 114: Icr Transmit Request Enable (Treq) Bit 1

    DMA transfers from host to DSP. In the other DMA modes, TREQ is ignored. Table 6-9 summarizes the effect of RREQ and TREQ on the HOREQ, HTRQ and HRRQ signals. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-20 INIT...

  • Page 115: Icr Double Host Request (Hdrq) Bit 2

    The HF1 bit is used as a general purpose flag for host-to-DSP communication. HF1 may be set or cleared by the host processor and cannot be changed by the DSP core. HF1 is reflected in the HSR on the DSP side of the HDI08. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor HTRQ signal...

  • Page 116: Icr Host Little Endian (Hlend) Bit 5

    DMA controller to supply the HA2, HA1, and HA0 address signals. For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively, DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-22...

  • Page 117: Cvr Host Vector (Hv[6:0]) Bits 0–6

    When the host command interrupt is recognized by the DSP interrupt control logic, the address of the interrupt routine taken is 2 ∗ HV. The host can write HC and HV in the same write cycle. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 118: Isr Transmit Data Register Empty (Txde) Bit 1

    TXDE is set when the contents of the transmit byte registers are transferred to the HORX register. TXDE is cleared when the transmit (TXL or TXH according to HLEND bit) register is DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-24...

  • Page 119: Isr Transmitter Ready (Trdy) Bit 2

    If the interrupt source has been enabled by the associated request enable bit in the ICR, HREQ is set if one or more of the two enabled interrupt sources is set. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 6-14 Host Request Status (HREQ) HTRQ and HRRQ deasserted;...

  • Page 120: Transmit Byte Registers (Txh:txm:txl)

    $7 clears the TXDE bit. The contents of the transmit byte registers are transferred as 24-bit data to the HORX register when both TXDE and the HRDF bit are cleared. This transfer operation sets TXDE and HRDF. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-26 Figure 6-15 Interrupt Vector Register (IVR)

  • Page 121: General Purpose Input/Output (Gpio)

    HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is set (see Section 6.5.8, "Host Data Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 6-15 Host Side Registers After Reset...

  • Page 122: Hdi08 Host Processor Data Transfer

    HC bit in the CVR to determine when the command has been accepted by the interrupt controller in the DSP core. When the command has been accepted for execution, the HC bit is cleared by the interrupt controller in the DSP core. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-28 Freescale Semiconductor...

  • Page 123: Servicing Interrupts

    HACK. The contents of the IVR are placed on the host data bus while HOREQ and HACK are simultaneously asserted. The IVR data tells the MC680XX host processor which interrupt routine to execute to service the DSP. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor STATUS...
  • Page 124 Servicing The Host Interface DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 6-30 Freescale Semiconductor...

  • Page 125: Serial Host Interface

    Generate the clock signal (in master mode) • Trigger DMA interrupts to service the transmit and receive events DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor C) bus. The SHI supports either bus protocol as either a slave or a...

  • Page 126: Shi Clock Generator

    HCKFR bit is set in the HCKR register. When the SHI operates in the slave mode, the clock is external and is input to the SHI (HMST = 0). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 C or the SPI bus protocols.

  • Page 127: Serial Host Interface Programming Model

    DSP side—see Side" through Section 7.4.6, "SHI Control/Status Register (HCSR)—DSP Side" information. Figure 7-3 SHI Programming Model—Host Side DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor HMST HMST = 0 Divide By 1 or 8 HMST = 1...

  • Page 128: Figure 7-4 Shi Programming Model-Dsp Side

    Serial Host Interface Programming Model Figure 7-4 SHI Programming Model—DSP Side DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 129: Shi Input/Output Shift Register (Iosr)—Host Side

    IOSR (see The IOSR cannot be accessed directly either by the host processor or by the DSP. It is fully controlled by the SHI controller logic. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 7-1...

  • Page 130: Shi Host Transmit Data Register (Htx)—Dsp Side

    R/W bit), but treats any following data bytes as regular data. That is, the SHI does not differentiate between its dedicated address and the general call address. HSAR cannot be accessed by the host processor. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 16-Bit Data Mode...

  • Page 131: Clock Phase And Polarity (Cpha And Cpol)—Bits 1–0

    The programmer may select any of four combinations of serial clock (SCK) phase and polarity when operating in the SPI mode (See Figure 7-6). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Serial Host Interface Programming Model C bus transfer.

  • Page 132: Figure 7-6 Spi Data-To-Clock Timing Diagram

    HTDE is set only at the end of the data word transmission. The master is responsible for deasserting and asserting the slave device SS line between word transmissions. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Internal Strobe for Data Capture NOTE...

  • Page 133: Hckr Divider Modulus Select (Hdm[7:0])—Bits 10–3

    C mode, the MISO line when in SPI master mode, and the MOSI line when in SPI slave mode). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor C when HCKFR is set. The HRS bit is cleared during hardware reset and...

  • Page 134: Shi Control/Status Register (Hcsr)—Dsp Side

    HEN is cleared. When operating in master mode, HEN should be cleared only when the SHI is idle (HBUSY = 0). HEN is cleared during hardware reset and software reset. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 7-10...

  • Page 135: Hcsr Serial Host Interface Mode (Hm[1:0])—Bits 3–2

    If HCKFR is cleared, any attempt from the master to execute a transfer when the slave is not ready results in an overrun or underrun error condition. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Serial Host Interface Programming Model C)—Bit 1...

  • Page 136: Hcsr Host-Request Enable (Hrqe[1:0])—Bits 8–7

    HRQE[1:0] are cleared during hardware reset and software reset. Table 7-5 HREQ Function In SHI Slave Modes HRQE1 HRQE0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 7-12 C and SPI modes. 21"). C bus by generating start events, clock pulses,...

  • Page 137: Hcsr Bus-Error Interrupt Enable (Hbie)—Bit 10

    HTIE and HTDE are set and HTUE is cleared, the SHI requests an SHI transmit-data interrupt service from the interrupt controller. If both HTIE and HTUE are set, the SHI requests an SHI DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Serial Host Interface Programming Model C master mode;...

  • Page 138: Hcsr Receive Interrupt Enable (Hrie[1:0])—Bits 13–12

    When operating in the SPI mode, HTUE is set at the first clock edge if CPHA = 1; it is set at the assertion of SS if CPHA = 0. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 7-14...

  • Page 139: Hcsr Host Transmit Data Empty (Htde)—Bit 15

    HROE is cleared by reading the HCSR with HROE set, followed by reading HRX. HROE is cleared by hardware reset, software reset, SHI individual reset, and during the stop state. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 140: Host Bus Error (Hber)—Bit 21

    C bus specifications, the standard mode (100 kHz clock rate) and a fast mode (400 kHz clock rate) are defined. The SHI can operate in either mode. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 7-16 C bus is busy (when in the I...

  • Page 141: Overview

    The acknowledging device must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable low during the high period of the acknowledge-related clock pulse (see Figure 7-9). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Data Line Change...

  • Page 142: Figure 7-9 Acknowledgment On The I C Bus

    This method is also used to provide indivisible data transfers. Various combinations of read/write formats are illustrated in Figure 7-10 Slave Address Start Figure 7-10 I DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 7-18 Figure 7-9 Acknowledgment on the I Figure 7-11. ACK from...

  • Page 143: Shi Programming Considerations

    It is recommended that an SHI individual reset (HEN cleared) be generated before beginning data reception in order to reset the HRX FIFO to its initial (empty) state (e.g., when switching from transmit to receive data). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ACK from...

  • Page 144: Spi Master Mode

    The HRX FIFO contains valid receive data, which the DSP can read with either DSP instructions or DMA transfers, if the HRNE status bit is set. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 7-20...

  • Page 145: I 2 C Slave Mode

    For this purpose, the slave device address byte does not count as part of the data; therefore, it is treated separately. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 146: Slave Mode

    IOSR for transmission. When asserted, HREQ indicates that the slave device is ready to transmit the next data word. HREQ is deasserted at the first clock pulse of the next transmitted data word. The HREQ line DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 7-22...

  • Page 147: I 2 C Master Mode

    When deasserted, HREQ prevents the clock generation of the next data word transfer until it is asserted again. Connecting DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor C master device.

  • Page 148: Master Mode

    SHI suspends the serial clock until new data is written into HTX (when the SHI proceeds with the transmit session) or HIDLE is set (the SHI reactivates the clock to generate the stop event and terminate the transmit session). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 7-24 C Master Mode...

  • Page 149: Shi Operation During Dsp Stop

    The HCSR and HCKR control bits are not affected. It is recommended that the SHI be disabled before entering the stop state. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor C mode, the SHI signals are disabled (high impedance state).
  • Page 150 SHI Programming Considerations NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 7-26 Freescale Semiconductor...

  • Page 151: Enhanced Serial Audio Interface (Esai)

    It is a superset of the 56300 Family ESSI peripheral and of the 56000 Family SAI peripheral. The DSP56366 has two ESAI modules. This section describes the ESAI, and Section 9 describes the ESAI_1. The ESAI and ESAI_1 share 4 data pins.

  • Page 152: Figure 8-1 Esai Block Diagram

    Introduction Clock / Frame Sync Generators Control Logic DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 RSMA RSMB Shift Register TSMA TSMB Shift Register RCCR TCCR SAICR Shift Register SAISR RCLK TCLK Figure 8-1 ESAI Block Diagram SDO0 [PC11]...

  • Page 153: Serial Transmit 2/Receive 3 Data Pin (Sdo2/Sdi3)

    If a data word follows immediately, there is no high-impedance interval. SDO2/SDI3 may be programmed as a general-purpose I/O pin (PC9) when the ESAI SDO2 and SDI3 functions are not being used. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ESAI Data and Control Pins...

  • Page 154: Serial Transmit 3/Receive 2 Data Pin (Sdo3/Sdi2)

    RCKD bit in the RCCR register.The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 155: Table 8-1 Receiver Clock Sources (Asynchronous Mode Only)

    TCKD bit in the TCCR register. The SCKT is a clock input or output used by all the enabled transmitters in the asynchronous mode (SYN=0) or by all the enabled transmitters and receivers in the synchronous mode (SYN=1) (see DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor NOTE...

  • Page 156: Frame Sync For Receiver (Fsr)

    IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. FSR may be programmed as a general-purpose I/O pin (PC1) when the ESAI FSR function is not being used. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Table 8-2 Transmitter Clock Sources Transmitter TCKD...

  • Page 157: Frame Sync For Transmitter (Fst)

    The ESAI can be viewed as five control registers, one status register, six transmit data registers, four receive data registers, two transmit slot mask registers, two receive slot mask registers and a DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 158: Tccr Transmit Prescale Modulus Select (Tpm7–Tpm0) - Bits 0–7

    The ESAI transmit clock generator functional diagram is shown in DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-2). In the synchronous mode (SYN=1), the bit clock defined for the...

  • Page 159: Tccr Transmit Prescaler Range (Tpsr) - Bit 8

    When TPSR is set, the fixed prescaler is bypassed. When TPSR is cleared, the fixed divide-by-eight prescaler is DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 160: Tccr Tx Frame Rate Divider Control (Tdc4–Tdc0) - Bits 9–13

    (TDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of 1 (TDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync (TFSL=1) must be used in this case. The ESAI frame sync generator functional diagram is shown in DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-10 NOTE Figure 8-4.

  • Page 161: Tccr Tx High Frequency Clock Divider (Tfp3-Tfp0) - Bits 14–17

    See The ESAI high frequency clock generator functional diagram is shown in Table 8-3 Transmitter High Frequency Clock Divider TFP3-TFP0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor RFSL INTERNAL RX FRAME CLOCK...

  • Page 162: Tccr Transmit Clock Polarity (Tckp) - Bit 18

    The read/write Transmit Control Register (TCR) controls the ESAI transmitter section. Interrupt enable bits for the transmitter section are provided in this control register. Operating modes are also selected in this register See Figure 8-5. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-12 Table Table 8-2.

  • Page 163: Tcr Esai Transmit 0 Enable (Te0) - Bit 0

    SDO1 pin remains in the high-impedance state. The on-demand mode transmit enable sequence can be the same as the normal mode, or TE1 can be left enabled. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 164: Tcr Esai Transmit 2 Enable (Te2) - Bit 2

    #4 is disabled after completing transmission of data currently in the ESAI transmit shift register. Data can be written to TX4 when TE4 is cleared but the data is not transferred to the transmit shift register #4. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-14 Freescale Semiconductor...

  • Page 165: Tcr Transmit Word Alignment Control (Twa) - Bit 7

    1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0), then the last data bit is repeated after the data word has been transmitted. If zero padding is enabled (PADC=1), zeroes are transmitted after the data word has been transmitted. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Figure 8-13 Figure 8-14).

  • Page 166: Tcr Transmit Network Mode Control (Tmod1-Tmod0) - Bits 8-9

    16 bits long, and the next 12 slots and words will be 20 bits long, as required by the AC97 protocol. Table 8-4 Transmit Network Mode Selection TMOD1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-16 Figure TMOD0...

  • Page 167: Figure 8-6 Normal And Network Operation

    ESAI Programming Model Figure 8-6 Normal and Network Operation DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor 8-17...

  • Page 168: Tcr Tx Slot And Word Length Select (Tsws4-Tsws0) - Bits 10-14

    Table Figure 8-14. Table 8-5 ESAI Transmit Slot and Word Length Selection TSWS4 TSWS3 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-18 8-5. See also the ESAI data path programming model in TSWS2 TSWS1 TSWS0 Figure 8-13...

  • Page 169: Tcr Transmit Frame Sync Length (Tfsl) - Bit 15

    The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a word-length frame sync is selected. If TFSL is set, a 1-bit clock period frame sync is selected. See Figure 8-7 for examples of frame length selection. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor TSWS2 TSWS1...

  • Page 170: Figure 8-7 Frame Length Selection

    RX SERIAL DATA DATA TX FRAME SYNC TX SERIAL DATA DATA DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-20 WORD LENGTH: TFSL=0, RFSL=0 ONE BIT LENGTH: TFSL=1, RFSL=1 MIXED FRAME LENGTH: TFSL=1, RFSL=0 MIXED FRAME LENGTH: TFSL=0, RFSL=1...

  • Page 171: Tcr Transmit Exception Interrupt Enable (Teie) - Bit 20

    When TEIE is cleared, this interrupt is disabled. Reading the SAISR status register followed by writing to all the data registers of the enabled transmitters clears TUE, thus clearing the pending interrupt. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor for more details.

  • Page 172: Tcr Transmit Even Slot Data Interrupt Enable (Tedie) - Bit 21

    The RCCR control bits are described in the following paragraphs (see X:$FFFFB8 RDC2 RDC1 RHCKD RFSD DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-22 Requests". Figure 8-8). RDC0...

  • Page 173: Rccr Receiver Prescale Modulus Select (Rpm7–Rpm0) - Bits 7–0

    When the HCKR input is being driven from an external high frequency clock, the RFP3-RFP0 bits specify an additional division ration in the clock divider chain. See ratio. The ESAI high frequency generator functional diagram is shown in DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor NOTE Figure 8-4.

  • Page 174: Rccr Receiver High Frequency Clock Polarity (Rhckp) - Bit 20

    RCKD is cleared, the clock source is external; the internal clock generator is disconnected from the SCKR pin, and an external clock source may drive this pin. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-24 Divide Ratio...

  • Page 175: Rccr Receiver Frame Sync Signal Direction (Rfsd) - Bit 22

    Buffer Enable, according to the TEBE control bit. If RFSD is cleared, then the FSR pin becomes the IF1 input flag. See Table 8-1 Table DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 8-1 Table 8-7 SCKR Pin Definition Table...

  • Page 176: Rccr Receiver High Frequency Clock Direction (Rhckd) - Bit 23

    Reserved bit - read as zero; should be written with zero for future compatibility. Hardware and software reset clear all the bits in the RCR register. The ESAI RCR bits are described in the following paragraphs. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-26 Table 8-9 HCKR Pin Definition Table...

  • Page 177: Rcr Receiver Shift Direction (Rshfd) - Bit 6

    RCR Receiver Shift Direction (RSHFD) - Bit 6 The RSHFD bit causes the receiver shift registers to shift data in MSB first when RSHFD is cleared or LSB first when RSHFD is set (see DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Figure 8-13 Figure 8-14).

  • Page 178: Rcr Receiver Slot And Word Select (Rsws4-Rsws0) - Bits 10-14

    ESAI. The word length must be equal to or shorter than the slot length. The possible combinations are shown in Table Figure 8-14. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-28 Figure RMOD0 RDC4-RDC0 Receiver Network Mode...

  • Page 179: Table 8-11 Esai Receive Slot And Word Length Selection

    Table 8-11 ESAI Receive Slot and Word Length Selection RSWS4 RSWS3 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor RSWS2 RSWS1 RSWS0 ESAI Programming Model SLOT LENGTH WORD LENGTH 8-29...

  • Page 180: Rcr Receiver Frame Sync Relative Timing (Rfsr) - Bit 16

    Note that to leave the personal reset state by clearing RPR, the procedure described in Initialization Examples" should be followed. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-30 RSWS2 RSWS1...

  • Page 181: Rcr Receive Even Slot Data Interrupt Enable (Redie) - Bit 21

    ESAI Common Control Register (SAICR) The read/write Common Control Register (SAICR) contains control bits for functions that affect both the receive and transmit sections of the ESAI.See DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Requests". Figure 8-10.

  • Page 182: Saicr Synchronous Mode Selection (Syn) - Bit 6

    The Synchronous Mode Selection (SYN) bit controls whether the receiver and transmitter sections of the ESAI operate synchronously or asynchronously with respect to each other (see is cleared, the asynchronous mode is chosen and independent clock and frame sync signals are used for DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-32 TEBE...

  • Page 183: Saicr Transmit External Buffer Enable (Tebe) - Bit 7

    While ALC is set, 20-bit and 24-bit words may not be used, and word length control should specify 8-, 12- or 16-bit words, otherwise results are unpredictable. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 8-7,...

  • Page 184: Esai Status Register (Saisr)

    ESAI Status Register (SAISR) The Status Register (SAISR) is a read-only status register used by the DSP to read the status and serial input flags of the ESAI. See Figure DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-34 ASYNCHRONOUS (SYN=0) TRANSMITTER...

  • Page 185: Saisr Receive Frame Sync Flag (Rfs) - Bit 6

    When set, RFS indicates that a receive frame sync occurred during reception of the words in the receiver data registers. This indicates that the data words are from the first slot in the frame. When RFS is clear and DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 186: Saisr Receive Even-Data Register Full (Redf) - Bit 9

    Data written to a transmit data register during the time slot when TFS is set is transmitted (in network mode), if the transmitter is enabled, DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-36...

  • Page 187: Saisr Transmit Even-Data Register Empty (Tede) - Bit 16

    N-1, where N is the number of time slots in the frame. This flag is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift registers; it is also set for a DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 188: Figure 8-13 Esai Data Path Programming Model ([R/T]Shfd=0)

    TRANSMIT HIGH BYTETRANSMIT MIDDLE BYTETRANSMIT LOW BYTE 0 7070 8-BIT DATA 12-BIT DATA 16-BIT DATA (b) Transmit Registers Figure 8-13 ESAI Data Path Programming Model ([R/T]SHFD=0) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-38 20-BIT DATA 24-BIT DATA NOTES: 20-BIT DATA 24-BIT DATA NOTES: 1.

  • Page 189: Figure 8-14 Esai Data Path Programming Model ([R/T]Shfd=1)

    TRANSMIT HIGH BYTETRANSMIT MIDDLE BYTETRANSMIT LOW BYTE 0 7070 8-BIT DATA 12-BIT DATA 16-BIT DATA (b) Transmit Registers Figure 8-14 ESAI Data Path Programming Model ([R/T]SHFD=1) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor 20-BIT DATA 24-BIT DATA NOTES: 16 BIT 12 BIT...

  • Page 190: Esai Transmit Data Registers (Tx5, Tx4, Tx3, Tx2,Tx1,Tx0)

    The Transmit Slot Mask Registers (TSMA and TSMB) are two read/write registers used by the transmitters in network mode to determine for each slot whether to transmit a data word and generate a DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-40...

  • Page 191: Figure 8-15 Tsma Register

    TSM setting. Data read from TSM returns the last written data. After hardware or software reset, the TSM register is preset to $FFFFFFFF, which means that all 32 possible slots are enabled for data transmission. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Figure 8-15 TSMA Register...

  • Page 192: Receive Slot Mask Registers (Rsma, Rsmb)

    RSM setting. Data read from RSM returns the last written data. After hardware or software reset, the RSM register is preset to $FFFFFFFF, which means that all 32 possible slots are enabled for data reception. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-42 NOTE...

  • Page 193: Operating Modes

    REx control bits will result in erroneous data being received as the first data word for the newly enabled receivers. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor NOTE...

  • Page 194: Esai Interrupt Requests

    (TDE=1), the slot is an even slot (TEDE=1), and no exception has occurred (TUE=0 or TEIE=0). Writing to all the TX registers of the enabled transmitters or to TSR clears this interrupt request. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-44 Freescale Semiconductor...

  • Page 195: Operating Modes – Normal, Network, And On-Demand

    When SYN is cleared, the ESAI transmitter and receiver clocks and frame sync sources are independent. If SYN is set, the ESAI transmitter and receiver clocks and frame sync come from the transmitter section (either external or internal sources). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Operating Modes...

  • Page 196: Shift Direction Selection

    Three ESAI pins (FSR, SCKR and HCKR) are available as serial I/O flags when the ESAI is operating in the synchronous mode (SYN=1). Their operation is controlled by RCKD, RFSD, TEBE bits in the RCR, DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-46...

  • Page 197: Gpio - Pins And Registers

    The read/write 24-bit Port C Direction Register (PRRC) in conjunction with the Port C Control Register (PCRC) controls the functionality of the ESAI GPIO pins. configurations. Hardware and software reset clear all PRRC bits. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 8-12 for the port pin configurations.

  • Page 198: Port C Data Register (Pdrc)

    PD[i] bit is reflected on this pin. If a port pin [i] is configured as disconnected, the corresponding PD[i] bit is not reset and contains undefined data. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-48...

  • Page 199: Initializing Just The Esai Transmitter Section

    It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI pin. • The transmitter section should be in its personal reset state (TPR = 1). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Figure 8-21 PDRC Register...

  • Page 200: Initializing Just The Esai Receiver Section

    Take the receiver section out of the personal reset state by clearing RPR. • Enable the receivers by setting their RE bits. • From now on the receivers are operating and can be serviced either by polling, interrupts, or DMA. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 8-50 Freescale Semiconductor...

  • Page 201: Enhanced Serial Audio Interface 1 (Esai_1)

    Enhanced Serial Audio Interface 1 (ESAI_1) Introduction The Enhanced Serial Audio Interface I (ESAI_1) is the second ESAI peripheral in the DSP56366. It is functionally identical to the ESAI peripheral described in Section 8, "Enhanced Serial AUDIO Interface (ESAI)" except for minor differences described in this section. Refer to the ESAI section for functional information about the ESAI_1, in addition to using the information in this section.

  • Page 202: Figure 9-1 Esai_1 Block Diagram

    TSMA_1 TSMB_1 RCCR_1 RCR_1 TCCR_1 TCR_1 SAICR_1 SAISR_1 TSR_1 Clock / Frame Sync Generators Control Logic DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 TX0_1 Shift Register TX1_1 Shift Register TX2_1 Shift Register RX3_1 TX3_1 Shift Register RX2_1 TX4_1...

  • Page 203: Serial Transmit 2/Receive 3 Data Pin (Sdo2_1/Sdi3_1)

    RX1_1 serial receive shift register when programmed as a receiver pin. SDO4_1/SDI1_1 may be programmed as a general-purpose pin (PE7) when the ESAI_1 SDO4_1 and SDI1_1 functions are not being used. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ESAI_1 Data and Control Pins...

  • Page 204: Serial Transmit 5/Receive 0 Data Pin (Sdo5_1/Sdi0_1)

    One status register • Six transmit data registers • Four receive data registers • Two transmit slot mask registers • Two receive slot mask registers • One special-purpose time slot register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 205: Esai_1 Transmitter Clock Control Register (Tccr_1)

    TCCR_1 also controls the number of words per frame for the serial data. Hardware and software reset clear all the bits of the TCCR_1 register. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 206: Tccr_1 Tx High Freq. Clock Divider (Tfp3-Tfp0) - Bits 14–17

    TCCR_1 Tx High Freq. Clock Direction (THCKD) - Bit 23 The ESAI_1 does not have the transmitter high frequency clock pin. THCKD must be set for proper ESAI_1 transmitter section operation. THCKD TFSD DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 TDC0 TPSR TPM7 TPM6...

  • Page 207: Figure 9-4 Esai_1 Clock Generator Functional Block Diagram

    FLAG0 OUT (SYNC MODE) SCKR_1 SYN=0 RCKD SCKT_1 TCKD THCKD=1 Figure 9-4 ESAI_1 Clock Generator Functional Block Diagram DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor PRESCALE DIVIDER DIVIDE DIVIDE BY DIVIDE BY BY 2 TO DIVIDE...

  • Page 208: Figure 9-6 Tcr_1 Register

    Reserved bit - read as zero; should be written with zero for future compatibility. Hardware and software reset clear all the bits in the TCR_1 register. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 RFSL INTERNAL RX FRAME CLOCK...

  • Page 209: Rccr_1 Rx High Freq. Clock Divider (Rfp3-Rfp0) - Bits 14–17

    The ESAI_1 does not have the receiver high frequency clock pin. RHCKD must be set for proper ESAI_1 receiver section operation. Table 9-3 Receiver Clock Sources (asynchronous mode only) RHCKD RFSD DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor RDC0 RPSR RPM7...

  • Page 210: Figure 9-9 Saicr_1 Register

    ESAI_1 Status Register (SAISR_1) The Status Register (SAISR_1) is a read-only status register used by the DSP to read the status and serial input flags of the ESAI_1. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 9-10 RSHFD REDIE...

  • Page 211: Figure 9-10 Saisr_1 Register

    8 most significant bits when ALC=1) of the TXx_1 are don’t care bits. The DSP is interrupted whenever the TXx_1 becomes empty if the transmit data register empty interrupt has been enabled. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 212: Figure 9-11 Tsma_1 Register

    (RDF=1), or to ignore the received data. RSMA_1 and RSMB_1 should be considered as each containing half of a 32-bit register RSM_1. See RSM_1 (RS**) is an enable/disable control bit for receiving data in slot number N. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 9-12 Figure 9-11 TSMA_1 Register...

  • Page 213: Figure 9-13 Rsma_1 Register

    (PRRE) controls the functionality of the ESAI_1 GPIO pins. Each of the PE(11:0) bits controls the functionality of the corresponding port pin. See software reset clear all PCRE bits. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Figure 9-13 RSMA_1 Register...

  • Page 214: Port E Direction Register (Prre)

    PD[i] bit will be reflected on this pin. If a port pin [i] is configured as disconnected, the corresponding PD[i] bit is not reset and contains undefined data. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 9-14...

  • Page 215: Figure 9-17 Pdre Register

    Y:$FFFF9D PD11 PD10 Reserved bit - read as zero; should be written with zero for future compatibility. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Figure 9-17 PDRE Register GPIO - Pins and Registers 9-15...
  • Page 216 GPIO - Pins and Registers NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 9-16 Freescale Semiconductor...

  • Page 217: Introduction

    When the DAX interrupts are disabled, they can still be served by DMA or by a “polling” technique. A block diagram of the DAX is shown in The shaded registers in instructions. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Figure 10-1.

  • Page 218: Dax Functional Overview

    • Non-audio data buffer (XNADBUF) • Audio and non-audio data shift register (XADSR) • Control register (XCTR) • Status register (XSTR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 10-2 Global Data Bus DMA Bus XADR XADBUFB XADBUFA C-U-V...

  • Page 219: Dax Programming Model

    The programmer-accessible DAX registers are shown in following subsections. The Interrupt Vector table for the DAX is shown in interrupt priority is shown in Table DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Figure 10-2. The registers are described in the 10-2.

  • Page 220: Dax Internal Architecture

    XADRA - Audio Data Register A - X:$FFFFD2 and XADRB - Audio Data Register B -X:$FFFFD3 XSTR - Status Register - X:$FFFFD4 18 17 16 Reserved bit DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 10-4 Table 10-1 DAX Interrupt Vectors Address...

  • Page 221: Dax Channel A Validity (Xva)—Bit 10

    DAX Channel A Validity (XVA)—Bit 10 The value of the XVA bit is transmitted as the twenty-ninth bit (Bit 28) of channel A subframe in the next frame. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor DAX Internal Architecture...

  • Page 222: Dax Channel A Channel Status (Xca)—Bit 12

    The XCTR is a 24-bit read/write register that controls the DAX operation. The contents of the XCTR are shown in Figure 10-2. XCTR is cleared by software reset and hardware reset. The XCTR bits are described in the following paragraphs. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 10-6 NOTE Freescale Semiconductor...

  • Page 223: Audio Data Register Empty Interrupt Enable (Xdie)—Bit 0

    Figure 10-2. XSTR is cleared by software reset, hardware reset an by the stop state. The XSTR bits are described in the following paragraphs. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 10-3 Clock Source Selection...

  • Page 224: Dax Transmit Underrun Error Flag (Xaur)—Bit 1

    10.5.7.4 XSTR Reserved Bits—Bits 3–23 These XSTR bits are reserved. They read as 0, and should be written with 0 to ensure compatibility with future device versions. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 10-8 #006 #007 #008...

  • Page 225: Dax Parity Generator (Prtyg)

    (64 × Fs). The clock source can be selected from the following options (see also Section 10.5.6.4, "DAX Clock Input Select (XCS[1:0])—Bits DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 10-4 Preamble Bit Patterns...

  • Page 226: Audio Data Register Empty Interrupt Handling

    When the XDIE bit is set and the DAX is active, an audio data register empty interrupt (XADE = 1) is generated once at the beginning of every frame transmission. Typically, within an XADE interrupt, the DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 10-10...

  • Page 227: Block Transferred Interrupt Handling

    $FFFFFE; offset=-2 The memory organization employed for DMA transfers depends on whether or not non-audio data changes from frame to frame as shown in DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Section 10.6.1, "Initiating A Transmit Session"...

  • Page 228: Gpio (Port D) - Pins And Registers

    DAX pin. When a PC[i] bit is cleared, the corresponding port pin is configured as GPIO pin. If both PC1 and PC0 are cleared, the DAX is disabled. Hardware and software reset clear all PCRD bits. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 10-12 $00000B...

  • Page 229: Port D Direction Register (Prrd)

    PD1 Input PD1 Input PD1 Input PD1 Output PD1 Output PD1 Output PD1 Output DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor 12 11 10 Table 10-6 describes the port pin configurations. 12 11 10 PDC0 GPIO (PORT D) - Pins and Registers...

  • Page 230: Port D Data Register (Pdrd)

    PD[i] bit will be reflected on the this pin. Hardware and software reset clear all PDRD bits. PDRD - Port D Data Register - X:$FFFFD5 20 19 18 read as zero, should be written with zero for future compatibility DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 10-14 PDC0 12 11 10...

  • Page 231: Introduction

    This section describes the internal timer/event counter in the DSP56366. Each of the three timers (timer 0, 1 and 2) can use internal clocking to interrupt the DSP56366 or trigger DMA transfers after a specified number of events (clocks). In addition, timer 0 provides external access via the bidirectional signal TIO0.

  • Page 232: Individual Timer Block Diagram

    (TCPR), and logic for clock selection and interrupt/DMA trigger generation. The timer mode is controlled by the TC[3:0] bits of the timer control/status register (TCSR). Timer modes are described in Section 11.4, "Timer Modes of DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 11-2 TPCR Timer Prescaler...

  • Page 233: Timer/Event Counter Programming Model

    11.3 Timer/Event Counter Programming Model The DSP56366 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space. Either standard polled or interrupt programming techniques can be used to service the timers. The timer programming model is shown in DSP56366 24-Bit Digital Signal Processor User Manual, Rev.

  • Page 234: Figure 11-3 Timer Module Programmer's Model

    Timer/Event Counter Programming Model TC1 TC0 TCF TOF - reserved, read as 0, should be written with 0 for future compatibility Figure 11-3 Timer Module Programmer’s Model DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 11-4 TCIE TOIE Timer Prescaler Load...

  • Page 235: Tplr Prescaler Preload Value Pl[20:0] Bits 20–0

    TIO0 signal. The external clock is internally synchronized to the internal clock. The external clock frequency must be lower than the DSP56366 internal operating frequency divided by 4 (CLK/4). The PS[1:0] bits are cleared by the hardware RESET signal or the software RESET instruction.

  • Page 236: Tpcr Prescaler Counter Value Pc[20:0] Bits 20–0

    The timer enable (TE) bit is used to enable or disable the timer. Setting TE enables the timer and clears the timer counter. The counter starts counting according to the mode selected by the timer control (TC[3:0]) bit values. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 11-6 Table 11-1 Prescaler Source Selection...

  • Page 237: Tcsr Timer Control (Tc[3:0]) Bits 4–7

    To ensure proper operation, the TC[3:0] bits should be changed only when the timer is disabled (when the TE bit in the TCSR has been cleared). DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Timer/Event Counter Programming Model NOTE Operation".

  • Page 238: Table 11-3 Timer Control Bits For Timers 1 And 2

    The GPIO function is enabled only if all of the TC[3:0] bits are zero. Table 11-3 Timer Control Bits for Timers 1 and 2 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 11-8 Table 11-2 Timer Control Bits for Timer 0...

  • Page 239: Tcsr Inverter (Inv) Bit 8

    — — — The INV bit is cleared by the hardware RESET signal or the software RESET instruction. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Table 11-4 Inverter (INV) Bit Operation INV = 1 GPIO signal on the TIO0...

  • Page 240: Tcsr Timer Reload Mode (Trm) Bit 9

    If the INV bit is set, the value of the DO bit is inverted when written to the TIO0 signal. When the INV bit is cleared, the value of the DO bit is written directly to the TIO0 signal. When GPIO mode is disabled, writing the DO bit has no effect. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 11-10 NOTE...

  • Page 241: Tcsr Prescaler Clock Enable (Pce) Bit 15

    11.3.4.13 TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23) These reserved bits are read as zero and should be written with zero for future compatibility. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Timer/Event Counter Programming Model...

  • Page 242: Timer Compare Register (Tcpr)

    — GPIO, mode 0: Internal timer interrupt generated by the internal clock — Pulse, mode 1: External timer pulse generated by the internal clock — Toggle, mode 2: Output timing signal toggled by the internal clock DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 11-12 Freescale Semiconductor...

  • Page 243: Timer Gpio (Mode 0)

    The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock can be taken from either the DSP56366 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.

  • Page 244: Timer Toggle (Mode 2)

    TIO0 signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the DSP56366 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter.

  • Page 245: Timer Event Counter (Mode 3)

    Timer 0 can be also be clocked from the TIO0 input signal. Each subsequent clock signal increments the counter. If an external clock is used, it must be internally synchronized to the internal clock and its frequency must be less than the DSP56366 internal operating frequency divided by 4.

  • Page 246: Measurement Input Width (Mode 4)

    (as determined by the INV bit) occurs on the TIO0 input pin, the counter is loaded with the TLR value on the first timer clock signal received either from the DSP56366 clock divided by two (CLK/2) or from the prescaler clock input. Each subsequent clock signal increments the counter.

  • Page 247: Measurement Input Period (Mode 5)

    After the first appropriate transition occurs on the TIO0 input pin, the counter is loaded with the TLR value on the first timer clock signal received from either the DSP56366 clock divided by two (CLK/2) or the prescaler clock output. Each subsequent clock signal increments the counter.

  • Page 248: Pulse Width Modulation (Pwm, Mode 7)

    Timer Modes of Operation clock signal can be taken from either the DSP56366 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter. At the first appropriate transition of the external clock detected on the TIO0 signal, the TCF bit in the TCSR is set and, if the TCIE bit is set, a compare interrupt is generated.

  • Page 249: Watchdog Pulse (Mode 9)

    Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TCPR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56366 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter.

  • Page 250: Timer Behavior During Wait

    TPCR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56366 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter. The TIO0 signal is set to the value of the INV bit.

  • Page 251: Timer Behavior During Stop

    TIO0 signal is disconnected. Any external changes that happen to the TIO0 signal is ignored when the DSP56366 is the stop state. To ensure correct operation, the timers should be disabled before the DSP56366 is placed into the stop state.
  • Page 252 Timer Modes of Operation NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 11-22 Freescale Semiconductor...

  • Page 253: Appendix A Bootstrap Rom Contents

    Appendix A Bootstrap ROM Contents DSP56366 Bootstrap Program ; BOOTSTRAP CODE FOR DSP56366 Rev. 0 silicon - (C) Copyright 1999 Motorola Inc. ; Revision 0.0 1999/JAN/26 - Modified from 56362_RevA_regular_boot_rev01.asm: - Change the length of xram and the length of yram - Change the address of the reserved area in the ;...
  • Page 254 ; If MD:MC:MB:MA=1110, then it loads the program RAM from the Host ; Interface programmed to operate in the 8051 multiplexed bus mode, ; in double-strob pin configuration. ; The HOST 8051 bootstrap code expects accesses that are byte wide. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...
  • Page 255 $D00000 AARV $D00409 PROMADDR equ $FF1000 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; this is the location in P memory ; on the external memory bus ; where the external byte-wide ; EPROM is located ;...
  • Page 256 ; MD:MC:MB:MA=0101 - Bootstrap from SHI (SPI slave) ; MD:MC:MB:MA=0110 - Bootstrap from SHI (I2C slave, HCKFR=1,100ns filter) ; MD:MC:MB:MA=0111 - Bootstrap from SHI (I2C slave, HCKFR=0) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 ; Address Attribute Register 1 ; OnCE GDB Register ;...
  • Page 257 #MB,omr,shi_loop <RESERVED ;======================================================================== ; This is the routine that loads from external EPROM. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; prepare SHI control value in r1 ; If MD:MC:MB:MA=01x0, go to SHI clock freeze ; If MD:MC:MB:MA=0101, select SPI mode ;...
  • Page 258 D - HC11 - Single strobe non-multiplexed bus with positive strobe pulse single negative request. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 ; r2 = address of external EPROM ; aar1 configured for SRAM types of access ; read number of words and starting address ;...
  • Page 259 <HDI08CONT OMR1IS0 jset #MA,omr,HC11HOSTLD ; If MD:MC:MB:MA=1101, go load from HC11 Host ISAHOSTLD movep #%0101000000011000,x:M_HPCR DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; Configure the following conditions: ; HAP = 0 Negative host acknowledge ; HRP = 0 Negative host request ;...
  • Page 260 HC11HOSTLD movep #%0000001000011000,x:M_HPCR <HDI08CONT I8051HOSTLD movep #%0001110000011110,x:M_HPCR DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 future compatability ; HEN = 0 When the HPCR register is modified HEN should be cleared ; HAEN = 0 Host acknowledge is disabled ;...
  • Page 261 ; expanded mode and jumps to the RESET vector. FINISH andi #$0,ccr jmp (r1) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; HROD = 0 Host request is active when enabled ; spare = 0 This bit should be set to 0 for future compatability ;...
  • Page 262 #SCKT,x:M_PCRC bset #SCKT,x:M_PRRC DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 A-10 ; IF MD:MC:MB:MA=1001, go to BURN ;; Port C GPIO Control Register ;; Port C GPIO Data Register ;; Port C Direction Register ;; SCKT is GPIO bit #3 in ESAI (Port C) ;;...
  • Page 263 #start_dram,r0 n0,_loopd move x:(r0),a1 x1,a DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor DSP56366 Bootstrap Program ;; r5 = test fail flag = $000000 ;; r7 = test pass flag = $FFFFFF ;; pattern for x memory ;;...
  • Page 264 <burn1 label1 bchg #SCKT,x:M_PDRC burn1 debug wait DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 A-12 ;; a0=a2=0 ;; accumulate error in b ;; x/y ram not symmetrical ;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b ;;...
  • Page 265 ; This code segment is located in the uppermost addresses of the Program ROM ORG PL:$FFB000-$14,PL:$FFB000-$14 move #$80000,r0 move #$0,x0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor DSP56366 Bootstrap Program ;; align for correct modulo addressing ; write address in unused Boot ROM location A-13...
  • Page 266 #$2,x0 move x0,x:(r0)+ move #$3,x0 move x0,x:(r0)+ move #$4,x0 move x0,x:(r0)+ move #$5,x0 move x0,x:(r0)+ move #$6,x0 move x0,x:(r0)+ move #$7,x0 move x0,x:(r0)+ move #$8,x0 move x0,x:(r0)+ DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 A-14 Freescale Semiconductor...

  • Page 267: Appendix B Equates

    I_VEC+$02 ; Stack Error I_ILL I_VEC+$04 ; Illegal Instruction I_IINST I_VEC+$04 ; Illegal Instruction I_DBG I_VEC+$06 ; Debug Request I_TRAP I_VEC+$08 ; Trap I_NMI I_VEC+$0A ; Non Maskable Interrupt DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...
  • Page 268 I_VEC+$30 ; ESAI Receive Data I_ESAIRED I_VEC+$32 ; ESAI Receive Even Data I_ESAIRDE I_VEC+$34 ; ESAI Receive Data With Exception Status DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 ; DAX Underrun Error ; DAX Block Transferred Freescale Semiconductor...
  • Page 269 ; TIMER 2 compare I_TIM2OF EQU I_VEC+$5E ; TIMER 2 overflow ;------------------------------------------------------------------------ ; HDI08 Interrupts ;------------------------------------------------------------------------ I_HI08RX EQU I_VEC+$60 ; Host Receive Data Full DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; SHI Bus Error Equates...
  • Page 270 ;********************************************************************************* page 132,55,0,0,0 ioequ ident ;------------------------------------------------------------------------ DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 ; ESAI_1 Receive Data ; ESAI_1 Receive Even Data ; ESAI_1 Receive Data With Exception Status ; ESAI_1 Receive Last Slot ; ESAI_1 Transmit Data ;...
  • Page 271 M_IPRP $FFFFFE Interrupt Priority Register Core (IPRC) M_IAL M_IAL0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; Host port GPIO data Register ; Host port GPIO direction Register ; Port C Control Register ; Port C Direction Register ;...
  • Page 272 $C0000 M_D3L0 M_D3L1 M_D4L $300000 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 ; IRQA Mode Interrupt Priority Level (high) ; IRQA Mode Trigger Mode ; IRQB Mode Mask ; IRQB Mode Interrupt Priority Level (low) ; IRQB Mode Interrupt Priority Level (high) ;...
  • Page 273 $C00 M_ESL10 M_ESL11 ;------------------------------------------------------------------------ EQUATES for Direct Memory Access (DMA) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; DMA4 Interrupt Priority Level (low) ; DMA4 Interrupt Priority Level (high) ; DMA5 Interrupt priority Level Mask ; DMA5 Interrupt Priority Level (low) ;...
  • Page 274 M_DSR3 $FFFFE3 M_DDR3 $FFFFE2 M_DCO3 $FFFFE1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 ; DMA Status Register ; DMA Offset Register 0 ; DMA Offset Register 1 ; DMA Offset Register 2 ; DMA Offset Register 3 ; DMA0 Source Address Register ;...
  • Page 275 M_DAM3 M_DAM4 M_DAM5 M_D3D M_DRS $F800 M_DRS0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; DMA3 Control Register ; DMA4 Source Address Register ; DMA4 Destination Address Register ; DMA4 Counter ; DMA4 Control Register ; DMA5 Source Address Register ;...
  • Page 276 M_DACT M_DCH $E00 M_DCH0 M_DCH1 M_DCH2 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-10 ;DMA Request Source bit 1 ;DMA Request Source bit 2 ;DMA Request Source bit 3 ;DMA Request Source bit 4 ; DMA Continuous Mode ;...
  • Page 277 $7000 M_DF0 M_DF1 M_DF2 M_XTLR M_XTLD M_PSTP DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; PLL Control Register ; Multiplication Factor Bits Mask (MF0-MF11) ;Multiplication Factor bit 0 ;Multiplication Factor bit 1 ;Multiplication Factor bit 2 ;Multiplication Factor bit 3...
  • Page 278 M_BA0W M_BA0W0 M_BA0W1 M_BA0W2 M_BA0W3 M_BA0W4 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-12 ; PLL Enable Bit ; PLL Clock Output Disable Bit ; PreDivider Factor Bits Mask (PD0-PD3) ;PreDivider Factor bit 0 ;PreDivider Factor bit 1 ;PreDivider Factor bit 2...
  • Page 279 DRAM Control Register M_BCW M_BCW0 M_BCW1 M_BRW DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; Area 1 Wait Control Mask (BA1W0-BA14) ;Area 1 Wait Control Bit 0 ;Area 1 Wait Control Bit 1 ;Area 1 Wait Control Bit 2 ;Area 1 Wait Control Bit 3...
  • Page 280 M_BAT1 M_BAAP M_BPEN M_BXEN M_BYEN DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-14 ;Out of Page Wait States bit 0 ; Out of Page Wait States bit 1 ; DRAM Page Size Bits Mask (BPS0-BPS1) ; DRAM Page Size Bits 0 ;...
  • Page 281 M_BAC8 M_BAC9 M_BAC10 M_BAC11 control and status bits in SR DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; Address Muxing ; Packing Enable ; Number of Address Bits to Compare Mask (BNC0-BNC3) ; Number of Address Bits to Compare 0 ;...
  • Page 282 M_EBD M_SD M_MS M_CDP $300 M_CDP0 M_CDP1 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-16 ; Scaling Bit ; Interupt Mask Bit 0 ; Interupt Mask Bit 1 ; Scaling Mode Bit 0 ; Scaling Mode Bit 1 ;...
  • Page 283 M_XNADR $FFFFD1 M_XCTR $FFFFD0 status bits in XSTR M_XADE M_XAUR DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; Burst Enable ; TA Synchronize Select ; Bus Release Timing ;Async. Bus Arbitration Enable ;Addess Priority Disable ;Address Tracing Enable ;...
  • Page 284 $FFFF92 M_HCSR $FFFF91 M_HCKR $FFFF90 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-18 ; DAX Block Transferred (XBLK) ; DAX Channel A Validity (XVA) ; DAX Channel A User Data (XUA) ; DAX Channel A Channel Status (XCA) ;...
  • Page 285 M_HCKFR M_HM1 M_HM0 M_HI2C M_HEN DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; SHI I2C Slave Address (HA6) ; SHI I2C Slave Address (HA5) ; SHI I2C Slave Address (HA4) ; SHI I2C Slave Address (HA3) ;...
  • Page 286 M_TSMB_1 EQU $FFFF9A M_TSMA_1 EQU $FFFF99 M_RCCR_1 EQU $FFFF98 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-20 ; SHI Filter Model (HFM1) ; SHI Filter Model (HFM0) ; SHI Divider Modulus Select (HDM7) ; SHI Divider Modulus Select (HDM6) ;...
  • Page 287 $FFFFBA M_TSMA $FFFFB9 M_RCCR $FFFFB8 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; ESAI_1 Receive Control Register (RCR_1) ; ESAI_1 Transmit Clock Control Register (TCCR_1) ; ESAI_1 Transmit Control Register (TCR_1) ; ESAI_1 Control Register (SAICR_1) ;...
  • Page 288 M_RS27 M_RS26 M_RS25 M_RS24 M_RS23 M_RS22 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-22 ; ESAI Receive Control Register (RCR) ; ESAI Transmit Clock Control Register (TCCR) ; ESAI Transmit Control Register (TCR) ; ESAI Control Register (SAICR) ;...
  • Page 289 M_RS4 M_RS3 M_RS2 M_RS1 M_RS0 TSMB Register bits M_TS31 M_TS30 M_TS29 M_TS28 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ;...
  • Page 290 M_TS12 M_TS11 M_TS10 M_TS9 M_TS8 M_TS7 M_TS6 M_TS5 M_TS4 M_TS3 M_TS2 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-24 ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ;...
  • Page 291 M_RDC2 M_RDC1 M_RDC0 M_RPSR M_RPM M_RPM7 M_RPM6 M_RPM5 M_RPM4 M_RPM3 M_RPM2 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ;ESAI ; ESAI ;ESAI ;ESAI MASK ; ESAI ;...
  • Page 292 $300 M_RMOD1 M_RMOD0 M_RWA M_RSHFD M_RE M_RE3 M_RE2 M_RE1 M_RE0 TCCR Register bits DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-26 ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ESAI ; ESAI ; ESAI ;ESAI MASK...
  • Page 293 M_TPM M_TPM7 M_TPM6 M_TPM5 M_TPM4 M_TPM3 M_TPM2 M_TPM1 M_TPM0 TCR Register bits DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; ESAI ; ESAI ; ESAI ;ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ;...
  • Page 294 M_TMOD0 M_TWA M_TSHFD M_TEM M_TE5 M_TE4 M_TE3 M_TE2 M_TE1 M_TE0 control bits of SAICR DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-28 ; ESAI ; ESAI ; ESAI ; ESAI ESAI ESAI ; ESAI ; ESAI ; ESAI ;...
  • Page 295 M_RFS M_IF2 M_IF1 M_IF0 ;------------------------------------------------------------------------ EQUATES for HDI08 ;------------------------------------------------------------------------ Register Addresses M_HOTX $FFFFC7 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ;ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ;...
  • Page 296 M_HF1 M_DMA HPCR bits M_HGEN M_HA8EN M_HA9EN DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-30 ; HOST Receive Register (HORX) ; HOST Base Address Register (HBAR) ; HOST Port Control Register (HPCR) ; HOST Status Register (HSR) ; HOST Control Register (HCR) ;...
  • Page 297 M_BA4 M_BA3 ;----------------------------------------------------------------------- EQUATES for TIMER ;------------------------------------------------------------------------ Register Addresses Of TIMER0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; HOST Chip Select Enable ; HOST Request Enable ; HOST Acknowledge Enable ; HOST Enable ; HOST Request Open Dranin mode ;...
  • Page 298 M_INV M_TRM M_DIR M_DI M_DO M_PCE ; Prescaled Clock Enable DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-32 ; TIMER0 Control/Status Register ; TIMER0 Load Reg ; TIMER0 Compare Register ; TIMER0 Count Register ; TIMER1 Control/Status Register ;...
  • Page 299 Timer Control Bits M_TC0 M_TC1 M_TC2 M_TC3 ;------------------ end of ioequ.asm ------------------------ DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor ; Timer Overflow Flag ; Timer Compare Flag ; Timer Control 0 ; Timer Control 1 ; Timer Control 2 ;...
  • Page 300 Equates NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 B-34 Freescale Semiconductor...

  • Page 301: Appendix C Jtag Bsdl

    HGND:linkage bit; SS_:in HREQ_:inout RESET_:in PVCC:linkage bit; PCAP:linkage bit; PGND:linkage bit; AA:out DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor J T A G S O F T W A R E bit; bit; bit; bit; bit;...
  • Page 302 15, " & "HSCKT: 16, " & "HSCKR: 17, " & "QVCC: (18, 56, 91, 126), " & "QGND: (19, 54, 90, 127), " & DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 bit; bit; bit; bit; bit; bit; bit; bit;...
  • Page 303 TAP_SCAN_OUT attribute TAP_SCAN_MODE attribute TAP_SCAN_CLOCK of attribute INSTRUCTION_LENGTH of DSP56366 : entity is 4; DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor "122, 123, 124, 125, 128, 131, 132, 133), " & TDI : signal is true;...
  • Page 304 "25 (BC_6, D(5), "26 (BC_6, D(4), "27 (BC_6, D(3), DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 of DSP56366 : entity is & -- version & -- manufacturer's use & -- sequence number & -- manufacturer identity -- 1149.1 requirement...
  • Page 305 (BC_1, AA(2), "76 (BC_1, *, "77 (BC_6, FST_1, "78 (BC_1, *, "79 (BC_6, SDO50_1, -- num cell port DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor control, 1)," & bidir, bidir, bidir, output3, output3, output3, control, 1)," &...
  • Page 306 (BC_1, *, "128 (BC_6, FSR, "129 (BC_1, *, "130 (BC_6, FST, "131 (BC_1, *, "132 (BC_6, SDOI50, DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 input, X)," & control, 1)," & bidir, control, 1)," & bidir, control, 1)," &...
  • Page 307 "147 (BC_6, SCK, "148 (BC_1, *, "149 (BC_6, SDA, "150 (BC_1, *, "151 (BC_6, MOSI, end DSP56366; DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor control, 1)," & bidir, 133, control, 1)," & bidir, 135, control, 1)," &...
  • Page 308 JTAG BSDL NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 309: Appendix D Programmer's Reference

    (HDI08). Table D-4 D.1.5 Programming Sheets The remaining figures describe major programmable registers on the DSP56366. Internal I/O Memory Map DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 310: Table D-1 Internal I/O Memory Map

    X:$FFFFE4 DMA3 X:$FFFFE3 X:$FFFFE2 X:$FFFFE1 X:$FFFFE0 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Table D-1. Internal I/O Memory Map Register Name INTERRUPT PRIORITY REGISTER CORE (IPR-C) INTERRUPT PRIORITY REGISTER PERIPHERAL (IPR-P) PLL CONTROL REGISTER (PCTL) ONCE GDB REGISTER (OGDB)
  • Page 311 X:$FFFFC2 X:$FFFFC1 X:$FFFFC0 PORT C X:$FFFFBF X:$FFFFBE X:$FFFFBD DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Register Name DMA SOURCE ADDRESS REGISTER (DSR4) DMA DESTINATION ADDRESS REGISTER (DDR4) DMA COUNTER (DCO4) DMA CONTROL REGISTER (DCR4) DMA SOURCE ADDRESS REGISTER (DSR5)
  • Page 312 X:$FFFF9E X:$FFFF9D X:$FFFF9C X:$FFFF9B X:$FFFF9A DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Register Name ESAI RECEIVE SLOT MASK REGISTER B (RSMB) ESAI RECEIVE SLOT MASK REGISTER A (RSMA) ESAI TRANSMIT SLOT MASK REGISTER B (TSMB) ESAI TRANSMIT SLOT MASK REGISTER A (TSMA)
  • Page 313 ESAI MUX PIN Y:$FFFFAF CONTROL Y:$FFFFAE Y:$FFFFAD Y:$FFFFAC Y:$FFFFAB Y:$FFFFAA Y:$FFFFA9 Y:$FFFFA8 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Register Name Reserved Reserved Reserved Reserved Reserved SHI RECEIVE FIFO (HRX) SHI TRANSMIT REGISTER (HTX) SHI I...
  • Page 314 Y:$FFFFA6 Y:$FFFFA5 Y:$FFFFA4 Y:$FFFFA3 Y:$FFFFA2 Y:$FFFFA1 Y:$FFFFA0 PORT E Y:$FFFF9F Y:$FFFF9E Y:$FFFF9D DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Register Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORT E CONTROL REGISTER (PCRE) PORT E DIRECTION REGISTER(PRRE)
  • Page 315 Y:$FFFF85 Y:$FFFF84 Y:$FFFF83 Y:$FFFF82 Y:$FFFF81 Y:$FFFF80 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Register Name ESAI_1 RECEIVE SLOT MASK REGISTER B (RSMB_1) ESAI_1 RECEIVE SLOT MASK REGISTER A (RSMA_1) ESAI_1 TRANSMIT SLOT MASK REGISTER B (TSMB_1)

  • Page 316: Interrupt Vector Addresses

    0 - 2 VBA:$3C 0 - 2 VBA:$3E 0 - 2 VBA:$40 0 - 2 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Table D-2. DSP56366 Interrupt Vectors Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non-Maskable Interrupt (NMI)
  • Page 317 VBA:$7E 0 - 2 VBA:$80 0 - 2 VBA:$FE 0 - 2 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor SHI Transmit Underrun Error SHI Receive FIFO Not Empty Reserved SHI Receive FIFO Full SHI Receive Overrun Error...

  • Page 318: Interrupt Source Priorities (Within An Ipl)

    Table D-3. Interrupt Sources Priorities Within an IPL Priority Level 3 (Nonmaskable) Highest Lowest Levels 0, 1, 2 (Maskable) Highest DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-10 Interrupt Source Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt...
  • Page 319 ESAI_1 Receive Even Data ESAI_1 Receive Data ESAI_1 Receive Last Slot ESAI_1 Transmit Data with Exception Status ESAI_1 Transmit Last Slot ESAI_1 Transmit Even Data Lowest ESAI_1 Transmit Data DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-11...

  • Page 320: Table D-4 Hdi08 Programming Model

    HCIE Host Command Interrupt Enable Host Flag 2 Host Flag 3 HDM[2:0] Host DMA Mode DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-12 Table D-4. HDI08 Programming Model Name Function DSP SIDE HRRQ interrupt disabled HRRQ interrupt enabled...
  • Page 321 Host Multiplxed Bus HDDS Host Dual Data Strobe HCSP Host Chip Select Polarity Host Request polarity Host Acknowledge Polarity DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Name Function GPIO pin disconnected GPIO pins active HA8/HA1 = GPIO...
  • Page 322 Host Flag 1 HLEND Host Little Endian HM1-HM0 Host Mode Control INIT Initialize DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-14 Name Function no receive data to be read receive data register is full transmit data register empty transmit data reg.

  • Page 323: Programming Sheets

    Host Transmit Data Register IV7-IV0 Interrupt Register Programming Sheets The worksheets shown on the following pages contain listings of major programmable registers for the DSP56366. The programming sheets are grouped into the following order: • Central Processor • Host Interface (HDI08) •...

  • Page 324: Figure D-1 Status Register (Sr

    3 (highest) 23 22 21 20 19 18 17 16 CP1 CP0 RM Extended Mode Register (MR) Read/Write Status Register (SR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-16 Carry Overfow Zero Negative Interrupt Mask I(1:0) Exceptions Masked...

  • Page 325: Figure D-2 Operating Mode Register (Omr

    WRP EOV EUN XYS MSW1 MSW0 System Stack Control Status Register (SCS) Operating Mode Register (OMR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Chip Operating Modes MOD(D:A) Reset Vector See Core Configuration Section. 15 14 13 12 11 10...

  • Page 326: Figure D-3 Interrupt Priority Register-Core (Ipr-C

    Programming Sheets Application: Figure D-3. Interrupt Priority Register–Core (IPR–C) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-18 Date: Programmer: Sheet 3 of 5 Freescale Semiconductor...

  • Page 327: Figure D-4 Interrupt Priority Register - Peripherals (Ipr-P

    Programming Sheets Date: Application: Programmer: Sheet 4 of 5 Figure D-4. Interrupt Priority Register – Peripherals (IPR–P) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-19...

  • Page 328: Figure D-5 Phase Lock Loop Control Register (Pctl

    Programming Sheets Application: Figure D-5. Phase Lock Loop Control Register (PCTL) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-20 Date: Programmer: Sheet 5 of 5 Freescale Semiconductor...

  • Page 329: Figure D-6 Host Receive And Host Transmit Data Registers

    Host Transmit Register (HOTX) X:$FFFEC7 Write Only Reset = empty Figure D-6. Host Receive and Host Transmit Data Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Host Receive Data (usually read by program) 15 14 13 12 11 10...

  • Page 330: Figure D-7 Host Control And Status Registers

    0 = DMA Mode Disabled 1 = DMA Mode Enabled Host Status Register (HSR) Figure D-7. Host Control and Status Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-22 1 = Enable if HRDF = 1 1 = Enable...

  • Page 331: Figure D-8 Host Base Address And Host Port Control

    Register (HPCR) X:$FFFFC4 Read/Write Reset = $0 = Reserved, Program as 0 Figure D-8. Host Base Address and Host Port Control DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor DSP Side BA10 X:$FFFFC5 Reset = $80 Host GPIO Port Enable...

  • Page 332: Figure D-9 Host Interrupt Control And Interrupt Status

    Read Only Host Request 0 = HOREQ Deasserted 1 = HOREQ Asserted Figure D-9. Host Interrupt Control and Interrupt Status DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-24 Processor Side 1 = Interrupts Enabled 1 = DSP -> Host 1 = Interrupts Enabled 1 = Host ->...

  • Page 333: Figure D-10 Host Interrupt Vector And Command Vector

    Contains Host Command Interrupt Address ÷ 2 Host Command Handshakes Executing Host Command Interrupts Figure D-10. Host Interrupt Vector and Command Vector DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor Processor Side Interrupt Vector Register (IVR) $3 R/W...

  • Page 334: Figure D-11 Host Receive And Transmit Byte Registers

    Transmit Byte Registers $7, $6, $5, $4 Write Only Reset = Empty Figure D-11. Host Receive and Transmit Byte Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-26 Processor Side Host Receive Data (HLEND = 0) Receive Middle Byte...

  • Page 335: Figure D-12 Shi Slave Address And Clock Control Registers

    Programming Sheets Date: Application: Programmer: Sheet 1 of 3 Figure D-12. SHI Slave Address and Clock Control Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-27...

  • Page 336: Figure D-13 Shi Transmit And Receive Data Registers

    Programming Sheets Application: Figure D-13. SHI Transmit and Receive Data Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-28 Date: Programmer: Sheet 2 of 3 Freescale Semiconductor...

  • Page 337: Figure D-14 Shi Host Control/Status Register

    Programming Sheets Date: Application: Programmer: Sheet 3 of 3 Figure D-14. SHI Host Control/Status Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-29...

  • Page 338: Figure D-15 Esai Transmit Clock Control Register

    Programming Sheets Application: Figure D-15. ESAI Transmit Clock Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-30 Date: Programmer: Freescale Semiconductor...

  • Page 339: Figure D-16 Esai Transmit Control Register

    Programming Sheets Date: Application: Programmer: Figure D-16. ESAI Transmit Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-31...

  • Page 340: Figure D-17 Esai Receive Clock Control Register

    Programming Sheets Application: Figure D-17. ESAI Receive Clock Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-32 Date: Programmer: Freescale Semiconductor...

  • Page 341: Figure D-18 Esai Receive Control Register

    Programming Sheets Date: Application: Programmer: Figure D-18. ESAI Receive Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-33...

  • Page 342: Figure D-19 Esai Common Control Register

    Programming Sheets Application: Figure D-19. ESAI Common Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-34 Date: Programmer: Freescale Semiconductor...

  • Page 343: Figure D-20 Esai Status Register

    Programming Sheets Date: Application: Programmer: Figure D-20. ESAI Status Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-35...

  • Page 344: Figure D-21 Esai_1 Multiplex Control Register

    Programming Sheets Application: Figure D-21. ESAI_1 Multiplex Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-36 Date: Programmer: Freescale Semiconductor...

  • Page 345: Figure D-22 Esai_1 Transmit Clock Control Register

    Programming Sheets Date: Application: Programmer: Figure D-22. ESAI_1 Transmit Clock Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-37...

  • Page 346: Figure D-23 Esai_1 Transmit Control Register

    Programming Sheets Application: Figure D-23. ESAI_1 Transmit Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-38 Date: Programmer: Freescale Semiconductor...

  • Page 347: Figure D-24 Esai_1 Receive Clock Control Register

    Programming Sheets Date: Application: Programmer: Figure D-24. ESAI_1 Receive Clock Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-39...

  • Page 348: Figure D-25 Esai_1 Receive Control Register

    Programming Sheets Application: Figure D-25. ESAI_1 Receive Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-40 Date: Programmer: Freescale Semiconductor...

  • Page 349: Figure D-26 Esai_1 Common Control Register

    Programming Sheets Date: Application: Programmer: Figure D-26. ESAI_1 Common Control Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-41...

  • Page 350: Figure D-27 Esai_1 Status Register

    Programming Sheets Application: DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-42 Figure D-27. ESAI_1 Status Register Date: Programmer: Freescale Semiconductor...

  • Page 351: Figure D-28 Dax Non-Audio Data Register

    Programming Sheets Date: Application: Programmer: Sheet 1 of 2 Figure D-28. DAX Non-Audio Data Register DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor D-43...

  • Page 352: Figure D-29 Dax Control And Status Registers

    Programming Sheets Application: Figure D-29. DAX Control and Status Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-44 Date: Programmer: Freescale Semiconductor...

  • Page 353: Figure D-30 Timer Prescaler Load And Prescaler Count Registers (Tplr, Tpcr

    TPCR:$FFFF82 Read Only Reset = $000000 Figure D-30. Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR) DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor 15 14 13 12 11 10 9 Prescaler Preload Value (PL [0:20])

  • Page 354: Figure D-31 Timer Control/Status Register

    1 = Counter wraparound has occurred 23 22 21 20 19 18 17 16 Timer Control/Status Register TCSR0:$FFFF8F Read/Write TCSR1:$FFFF8B Read/Write TCSR2:$FFFF87 Read/Write Reset = $000000 DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-46 TC (3:0) 0000 0001 0010 0011 0100...

  • Page 355: Figure D-32 Timer Load, Compare And Count Registers

    TCR1:$FFFF88 Read Only TCR2:$FFFF84 Read Only Reset = $000000 Figure D-32. Timer Load, Compare and Count Registers DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor 15 14 13 12 11 10 9 Timer Reload Value 15 14 13 12 11 10 9...

  • Page 356: Figure D-33 Gpio Port B

    Dx holds value of corresponding HDI08 GPIO pin. Function depends on HDDR. See the HDI08 HPCR Register (Figure D-8) for additional Port B GPIO control bits. DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-48 Port B (HDI08) DR12...

  • Page 357: Figure D-34 Gpio Port C

    If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...

  • Page 358: Figure D-35 Gpio Port D

    If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-50...

  • Page 359: Figure D-36 Gpio Port E

    If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor...
  • Page 360 Programming Sheets NOTES DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 D-52 Freescale Semiconductor...

  • Page 361: Dsp56366 24-Bit Digital Signal Processor, Rev

    DAX Status Register (XSTR) 7 DAX Transmit Underrun error (XAUR) status flag DI 10 Digital Audio Transmitter 1, 21 Digital Audio Transmitter (DAX) 10, 1 DIR 10 Divide Factor (DF) 7 DMA 6 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Index-1...
  • Page 362 Master Mode 23 Protocol for Host Write Cycle 18 Receive Data In Master Mode 24 Receive Data In Slave Mode 21 Slave Mode 21 Start and Stop Events 17 DSP56366 24-Bit Digital Signal Processor, Rev. 4 C/SPI Selec- Freescale Semiconductor...
  • Page 363 Program Counter register (PC) 6 Program Data Bus (PDB) 6 Program Decode Controller (PDC) 5 Program Interrupt Controller (PIC) 5 Program Memory Expansion Bus 6 Programming Model SHI—DSP Side 4 SHI—Host Side 3 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Index-3...
  • Page 364 Stack Pointer (SP) 6 Status Register (SR) 6 System Stack (SS) 6 SZ register 6 TAP 7 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Bus Error 16 Host Busy 16 Host Receive FIFO Full 15 Host Receive FIFO Not Empty 15...
  • Page 365 X Memory Expansion Bus 6 XAB 6 XDB 6 Y Memory Address Bus (YAB) 6 Y Memory Data Bus (YDB) 6 Y Memory Expansion Bus 6 YAB 6 YDB 6 DSP56366 24-Bit Digital Signal Processor, Rev. 4 0-20—Prescaler Load Value (PL0-PL20) 5 bits Index-5...
  • Page 366 DSP56366 24-Bit Digital Signal Processor, Rev. 4 Index-6 Freescale Semiconductor...

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