Freescale Semiconductor e200z3 Reference Manual page 219

Priority Exception
17 Program: trap
System call
SPE floating-point data
SPE round
18 Alignment
19 Debug with concurrent
DTLB or data storage
interrupt:
2
1. DAC/IAC linked
2
2. DAC unlinked
20 Data TLB error
21 Data storage
22 1. Debug: IRPT
2. Debug: CIRPT
23 1. Debug: DAC/IAC linked
2. Debug: DAC unlinked
24 Debug: ICMP
1
These exceptions are sampled at instruction boundaries, and may actually occur after exceptions that are due to a currently
executing instruction. If one of these exceptions occurs during execution of an instruction in the pipeline, it is not processed
until the pipeline has been flushed, and the exception associated with the excepting instruction may occur first.
2
When no data storage interrupt or data TLB error occurs, the core implements the data address compare debug exceptions
as post-instruction exceptions, which differs from the Book E definition. When a TEA (either a DTLB error or data storage
interrupt) occurs in conjunction with an enabled DAC or linked DAC/IAC on a load or store class instruction, the debug interrupt
takes priority, and the saved PC value points to the load or store class instruction, rather than to the next instruction.
Freescale Semiconductor
Table 4-32. e200z3 Exception Priorities (continued)
Condition specified in tw or twi instruction met and not a debug trap exception
Execution of the system call (sc, se_sc) instruction.
NaN, infinity, or denormalized data detected as input or output, or underflow,
overflow, divide by zero, or invalid operation in the SPE APU.
Inexact result
lmw, stmw, lwarx, or stwcx. Not word aligned. dcbz with cache disabled or not
present
Debug with concurrent DTLB or data storage interrupt. DBSR[IDE] also set.
1. Data address compare linked with instruction address compare
2. Data address compare unlinked
Note: Exceptions require corresponding debug event enabled, MSR[DE]=1, and
DBCR0[IDM]=1. In this case, the debug exception is considered imprecise and
DBSR[IDE] is set. Saved PC points to the load or store instruction causing the
DAC event.
Data translation lookup miss in the TLB.
1. Access control.
2. Byte ordering due to misaligned access across page boundary to pages with
mismatched E bits.
3. Precise external termination error ( p_tea_b assertion and precise
recognition) and MSR[EE]=1
1. Interrupt taken (non-critical)
2. Critical interrupt taken (critical only)
Note: Exceptions require corresponding debug event enabled, MSR[DE]=1 and
DBCR0[IDM]=1.
Post-Instruction Execution Exceptions
2
1. Data address compare linked with instruction address compare
2
2. Data address compare unlinked
Notes:
• Exceptions require corresponding debug event enabled, MSR[DE] = 1 and
DBCR0[IDM] = 1.
• Saved PC points to the instruction following the load or store instruction
causing the DAC event.
• For DVC DAC events in e200z335, the saved PC may point beyond the next
instruction, and the DBSR[DAC_OFST] field will indicate the offset.
Completion of an instruction.
Note: Exceptions require corresponding debug event enabled, MSR[DE]=1, and
DBCR0[IDM]=1.
e200z3 Power Architecture Core Reference Manual, Rev. 2
Interrupts and Exceptions
Cause IVOR
15
8
33
34
5
15
13
2
15
15
15
4-31