Freescale Semiconductor e200z3 Reference Manual page 326

External Core Complex Interfaces
7.5.6 Interrupt Interface
Figure 7-30 shows the relationship of the interrupt input signals to the CPU clock. The p_avec_b,
p_extint_b, p_critint_b, and p_voffset[0:15] inputs must meet setup and hold timing relative to the rising
edge of m_clk. In addition, during each clock cycle in which either p_extint_b or p_critint_b is asserted,
p_avec_b and p_voffset[0:15] are required to be in a valid state for the highest priority interrupt requested.
m_clk
p_extint_b
p_critint_b
p_avec_b
p_voffset[0:15]
Figure 7-30. Interrupt Interface Input Signals
Figure 7-31 shows the relationship between p_ipend and the interrupt request inputs. Note that p_ipend is
asserted combinationally from the p_extint_b and p_critint_b inputs.
m_clk
p_extint_b
p_critint_b
Exception vector fetch
p_ipend
Figure 7-31. Interrupt Pending Operation
e200z3 Power Architecture Core Reference Manual, Rev. 2
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