Freescale Semiconductor e200z3 Reference Manual page 439

Index
write-through mode (W bit), 2-57
mfspr
and MAS registers, 5-10
Misalignment in accesses, 3-1
MMUCFG (MMU configuration register), 2-52
MMUCSR0 (MMU control and status register), 2-52
MSCR (machine check syndrome register), 4-7
MSR (machine state register), 2-6, 4-5, 9-29
msync, 3-4, 4-32
mtspr
and MAS registers, 5-10
N
Nap mode, see Power management
Nexus3 module
access to memory-mapped resources, 10-42
block read access (burst mode), 10-45
block read access (non-burst), 10-45
block write access (burst mode), 10-43
block write access (non-burst), 10-43
single read access, 10-44
single write access, 10-42
auxiliary port
arbitration, 10-51
rules for output messages, 10-51
block diagram, 10-4
branch trace messaging (BTM)
data trace timing diagrams, 10-39
direct branch message instructions, 10-24
for program tracing, 10-24
indirect branch message instructions, 10-24
message formats, 10-25–10-30
BTM overflow error messages, 10-28
debug status messages, 10-27
direct branch messages (traditional), 10-26
indirect branch messages (history), 10-26
indirect branch messages (traditional), 10-26
program correlation messages, 10-27
program trace synchronization messages, 10-29
resource full messages, 10-26
operation, 10-31
branch/predicate instruction history (HIST), 10-32
enabling program trace, 10-31
program trace queueing, 10-32
relative addressing, 10-31
sequential instruction count (I-CNT), 10-32
program trace timing diagrams, 10-33–10-34
using branch history messages, 10-25
using tranditional program trace messages, 10-25
data trace messaging (DTM)
message formats, 10-34–10-37
data read messages, 10-35
Freescale Semiconductor
e200z3 Power Architecture Core Reference Manual, Rev. 2
data trace synchronization messages, 10-36
data write messages, 10-34
DTM overflow error messages, 10-35
operation
data access/instruction access data tracing, 10-38
data trace windowing, 10-38
DTM queueing, 10-37
relative addressing, 10-38
special cases (bus cycles), 10-38
error handling
access termination, 10-46
AHB read/write error, 10-46
read/write access error message, 10-46
example messages, 10-51
features, 10-2
IEEE 1149.1 (JTAG) sequences
reads of memory-mapped resources, 10-55
writes of memory-mapped resources, 10-55
operation
enabling Nexus3 module, 10-4
register access through JTAG/OnCE, 10-21
TCODEs supported, 10-5
ownership trace messaging (OTM), 10-22
error messages, 10-23
OTM flow, 10-23
programming model, 10-9
registers
client select control (CSC), 10-10
data trace control (DTC), 10-19
data trace end address 1, 2 (DTEA1, DTEA2), 10-20
data trace start address 1, 2 (DTSA1, DTSA2), 10-20
development control (DC1, DC2), 10-12
development status (DS), 10-14
port configuration (PCR), 10-10
read/write access address (RWA), 10-17
read/write access control/status (RWCS), 10-14
read/write access data (RWD), 10-16
watchpoint trigger (WT), 10-18
signal interface, 10-46
protocol, 10-48
terms and definitions, 10-1
watchpoint messaging, 10-40–10-41
error message format, 10-41
watchpoint timing diagrams, 10-41
O
OCMR (OnCE command register), 9-17
OCR (OnCE control register), 9-20
OnCE controller interface
signals, 9-13
external, 9-14
internal, 9-14
N–O
Index-5