Freescale Semiconductor e200z3 Reference Manual page 291

Table 7-17. Descriptions of Debug Events Signals (continued)
Signal I/O
p_devt1 I External debug event 1. Used to request an external debug event. If the core clock is disabled, this signal is not
recognized. In addition, only a transition from negated to asserted state of p_devt1 causes an event to occur. It is
intended to signal core-related events generated while the CPU is active.
State Asserted—An external debug event is requested. Only a transition from negated to asserted state of
Meaning
Negated—No external debug event is requested.
Timing Not internally synchronized by the core, and must meet setup and hold time constraints relative to
m_clk when the core clock is running.
p_devt2
I External debug event 2. Used to request an external debug event. If the core clock is disabled, this signal is not
recognized. In addition, only a transition from negated to asserted state of p_devt2 causes an event to occur. It is
intended to signal core-related events generated while the CPU is active.
State Asserted—An external debug event is requested. Only a transition from negated to asserted state of
Meaning
Negated—No external debug event is requested.
Timing Not internally synchronized by the core, and must meet setup and hold time constraints relative to
m_clk when the core clock is running.
Table 7-18 lists debug/emulation (Nexus 1/ OnCE) support signals. These signals assist in implementing
an on-chip emulation capability with a controller external to the
Signal
jd_en_once
jd_debug_b
jd_de_b
jd_de_en
jd_mclk_on
Freescale Semiconductor
p_devt1 causes an event to occur. It is intended to signal core-related events generated while the
CPU is active.
p_devt2 causes an event to occur.
Table 7-18. Core Debug/Emulation Support Signals
Type
I Enable full OnCE operation
O Debug session indicator
I Debug request
O DE_b active high output enable
I CPU clock is active indicator
e200z3 Power Architecture Core Reference Manual, Rev. 2
Signal Description
.
core
Description
External Core Complex Interfaces
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