Freescale Semiconductor e200z3 Reference Manual page 442

U–X
timer control register (TCR), 2-28
timer status register (TSR), 2-29
TLB concept, see Memory management unit (MMU)
TLBnCFG (TLB configuration registers 0–1), 2-53, 5-14
TLBs (translation lookaside buffers)
entry field definitions, 5-9
interrupts, 5-2
IPROT (protection from invalidation) field, 5-8
maintenance features
programming model, 5-1
miss exception not taken, 5-8
registers, 5-2
True little-endian pages, 2-57
TSR (timer status register), 2-29
U
Unsupported instructions and instruction forms, 3-2
User instruction set architecture (UISA) description, 1-xxvii
USPRG0 (user SPR), 2-26
W
Watchdog timer
watchdog timer interrupt, 4-19
see also Interrupt handling
Watchpoint messaging, see Nexus3 module
Watchpoint signaling, see Debug facilities
WBBR (write-back bus register), 9-28
WIMGE bits
see Memory/cache access attributes (WIMGE bits), 5-9
WT (watchpoint trigger register), 10-18
X
XER (integer exception register), 2-10
Index-8
e200z3 Power Architecture Core Reference Manual, Rev. 2
Index
Freescale Semiconductor