Freescale Semiconductor e200z3 Reference Manual page 356

Debug Support
Table 9-9. OnCE Register Access Requirements (continued)
Register
Name jd_en_once
to be Set
OCR Y
OSR Y
PC FIFO Y
Cache debug Y
access control
(CDACNTL)
Cache debug Y
access data
(CDADATA)
Nexus3-Acces Y
s
External GPRs Y
LSRL Select Y
1
Writes to these registers while the CPU is running may have unpredictable results due to the pipelined nature of the operation
and the fact that updates are not synchronized to a particular clock, instruction, or bus cycle boundary; therefore, it is strongly
recommended to ensure the processor is first placed into debug mode before updates to these registers are performed.
9.5.7 Methods for Entering Debug Mode
The OSR indicates that the CPU has entered the debug mode through the debug status bit. The following
sections describe how debug mode is entered assuming the OnCE circuitry has been enabled. OnCE
operation is enabled by the assertion of the jd_en_once input (see
9-24
Access Requirements
m_clk CPU to
DBCR0
active be Halted
[EDM]
for Write for Read
= 1
Access Access
N N N
N — N
N — N
N Y Y
N Y Y
N N N
N N N
N ? ?
e200z3 Power Architecture Core Reference Manual, Rev. 2
CPU to
be Halted
for Write
Access
N
— Read only, accessed by scanning out IR while
jd_en_once is set
— Read only, updates frozen while OCMD holds
PCFIFO register encoding
Note: PCFIFO cannot be updated while the
OnCE state machine is in Test_Logic_Reset state
Y CPU must be in debug mode with clocks running
Y CPU must be in debug mode with clocks running
N
N
? System test logic implementation determines
LSRL functionality
Table 9-2).
Notes
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