Debug Control Register 1 (Dbcr1) - Freescale Semiconductor e200z3 Reference Manual

Bits Name
56 DCNT2 Debug counter 2 debug event enable.
0 counter 2 debug events are disabled.
1 counter 2 debug events are enabled.
57 CIRPT Critical interrupt taken debug event enable.
0 CIRPT debug events are disabled.
1 CIRPT debug events are enabled.
58 CRET Critical return debug event enable.
0 CRET debug events are disabled.
1 CRET debug events are enabled.
59 VLES VLE status, Set if an ICMP, BRT, TRAP, RET, CRET, IAC, or DAC debug event occurred on a VLE instruction.
Undefined for IRPT, CIRPT, DEVT[1,2], DCNT[1,2], and UDE events.
60–62 — Reserved.
63 FT Freeze timers on debug event.
0 Timebase timers are unaffected by set DBSR bits.
1 Disable clocking of timebase timers if any DBSR bit is set (except MRR or CNT1TRG).
2.12.3.2

Debug Control Register 1 (DBCR1)

DBCR1, shown in Figure
32 33 34 35
Field IAC1US IAC1ER IAC2US IAC2ER IAC12M
Reset
R/W
SPR
1
Reset by processor reset p_reset_b if DBCR0[EDM]=0, as well as unconditionally by m_por. If DBCR0[EDM]=1,
DBERC0 masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated
by DBERC0 will be reset by p_reset_b.
Freescale Semiconductor
Table 2-17. DBCR0 Field Descriptions (continued)
2-34, is used to configure instruction address compare operation.
36 37 38 39 40 41 42
Figure 2-34. Debug Control Register 1 (DBCR1)
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
47 48 49 50 51 52
— IAC3US IAC3ER IAC4US IAC4ER IAC34M
1
All zeros
R/W
SPR 309
Register Model
53 54 55 56 57 58
—
63
2-39