Freescale Semiconductor e200z3 Reference Manual page 310

Power architecture core
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External Core Complex Interfaces
m_clk
p_htrans
p_addr,p_hprot
p_hsize ,
p_hbstrb , etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
Figure 7-13. Misaligned Write, Single Cycle Read Transfer, Full Pipelining
7-42
1
2
nonseq
nonseq
addr x
addr x+
single
single
data x
okay
e200z3 Power Architecture Core Reference Manual, Rev. 2
3
nonseq
addr y
single
**
data x+
okay
okay
4
5
idle
data y
okay
Freescale Semiconductor

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