Freescale Semiconductor e200z3 Reference Manual page 285

Table 7-10 describes the master ID configuration signals. These inputs drive the p_[d,i]_hmaster[3:0]
outputs when a bus cycle is active.
Table 7-10. Descriptions of Master ID Configuration Signals
Signal I/O
p_masterid[3:0] I CPU master. Configures the master ID for the CPU. Driven on p_[d,i]_hmaster[3:0] for a CPU-initiated
bus cycle.
nex_masterid[3:0] I Nexus3 master. Configure the master ID for the Nexus3 unit. Driven on p_[d,i]_hmaster[3:0] for a
Nexus3-initiated bus cycle.
Table 7-11 describes interrupt control signals. Interrupt request inputs (p_extint_b, p_critint_b, and
p_mcp_b) to the core are level-sensitive. The interrupt controller must keep the interrupt request and any
p_voffset or p_avec_b inputs (as appropriate) asserted until the interrupt is serviced to guarantee that the
core recognizes the request. On the other hand, when a request is generated, the core may still not
recognize the interrupt request, even if it is removed later. Requests must be held stable to avoid spurious
responses.
Signal I/O
p_extint_b External input interrupt request. Provides the external input interrupt request to the core. p_extint_b is
I
masked by MSR[EE].
State
Meaning
Timing Not internally synchronized by the core. It must meet setup and hold time constraints relative
p_critint_b I Critical input interrupt request. Critical input interrupt request to the core. Masked by MSR[CE].
State
Meaning
Timing Not internally synchronized by the core. Must meet setup and hold times relative to m_clk when
p_ipend I Interrupt pending. Indicates whether a p_extint_b or p_critint_b interrupt request or an enabled timer
facility interrupt was recognized internally by the core, is enabled by the appropriate MSR bit, and is
asserted in response to the interrupt request inputs.
p_ipend can signal other bus masters or a bus arbiter that an interrupt is pending. External power
management logic can use p_ipend to control operation of the core and other logic or may use p_wakeup
similarly. Higher priority exceptions may delay handling of the interrupt.
State
Meaning
Freescale Semiconductor
Table 7-11. Descriptions of Interrupt Signals
Asserted—An external input interrupt request has been signaled.
Negated—An external input interrupt request has not been signaled.
to m_clk when the core clock is running.
Assertion—Level-sensitive, must remain asserted to be guaranteed recognition.
Asserted—Critical input interrupt is being requested.
Negated—No critical input interrupt is requested.
the core clock is running. See
Assertion—Level-sensitive, must remain asserted to be guaranteed to be recognized.
Asserted—A p_extint_b or p_critint_b interrupt request or an enabled timer facility interrupt
(watchdog, fixed-Interval, or decrementer) was recognized internally by the core.
Assertion of p_ipend does not mean that exception processing for the interrupt has
begun.
Negated—A p_extint_b or p_critint_b interrupt request or an enabled timer facility interrupt has
not been recognized.
e200z3 Power Architecture Core Reference Manual, Rev. 2
Signal Description
Signal Description
Section 7.5.6, "Interrupt Interface."
External Core Complex Interfaces
7-17