Freescale Semiconductor e200z3 Reference Manual page 403

Power architecture core
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Error information is messaged out in the format shown in
(5 bits)
Error Code (00010/00111/01000
10.8.2.4
Data Trace Synchronization Messages
A data trace write/read with synchronization message is messaged through the auxiliary port, provided
data trace is enabled, for the following conditions (see
Initial data trace message after exit from system reset or whenever data trace is enabled
Upon returning from a CPU low-power state
Upon returning from debug mode
After occurrence of queue overrun (can be caused by any trace message), provided data trace is
enabled
After the periodic data trace counter has expired, indicating 255 data trace messages have occurred
without synchronization since the last with-synchronization message occurred
Upon assertion of the event-in nex_evti_b pin, the first data trace message is a synchronization
message if the EIC bits of the DC1 register have enabled this feature.
Upon data trace write/read after the previous DTM message was lost due to an attempted access to
a secure memory location (for SOC's with security)
Upon data trace write/read after the previous DTM message was lost due to a collision entering the
FIFO between the DTM message and any of the following:
— watchpoint message
— ownership trace message
— branch trace message
Data trace synchronization messages provide the full address, without leading zeros, and ensure that
development tools fully synchronize with data trace regularly. Synchronization messages provide a
reference address for subsequent DTMs, in which only the unique portion of the data trace address is
transmitted. The format for data trace write/read with synchronization messages is as follows:
(1–64 bits)
Data Value
Figure 10-35. Data Write/Read with Synchronization Message Format
Freescale Semiconductor
(4 bits)
Source Process
Fixed length = 15 bits
Figure 10-34. Error Message Format
(1–32 bits)
Full Address
Maximum length = 109 bit; Minimum length = 15 bits
e200z3 Power Architecture Core Reference Manual, Rev. 2
Figure
10-34:
(6 bits)
TCODE (001000)
Table
10-25):
(3 bits)
(4 bits)
Data
Source
Size
Process
Nexus3/Nexus2+ Module
(6 bits)
TCODE
(001101 or 001110)
10-37

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