Freescale Semiconductor e200z3 Reference Manual page 306

External Core Complex Interfaces
m_clk
p_htrans
p_addr,p_hprot
p_hsize ,
p_hbstrb , etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
Figure 7-9. Multiple-Cycle Reads with Wait-State, Single-Cycle Writes, Full Pipelining
The first read request (addr
(addr ) is not taken at the end of cycle C2 because no ready response is signaled and only one access can
y
be outstanding (addr ). It is taken at the end of C3 once the first read request has signaled a ready/OKAY
x
response.
The first write request (addr
for the second read access (addr
access is terminating.
Data for the addr write cycle is driven in C6, the cycle after the access is taken. During C6, the addr
z
access is terminated and the addr
During C7, data for the addr
the write cycle to addr .
w
Figure 7-10 shows another sequence of read and write cycles. In this example, reads incur a single wait
state.
7-38
1 2 3
nonseq nonseq
addr x addr y
single single
data x
okay okay okay
) is taken at the end of cycle C1 because the bus is idle. The second read request
x
) is not taken during C4 because a ready response is not asserted during C4
z
). During C5, the request for a write to addr
y
write request is taken.
w
write access is driven, and a ready/OKAY response is asserted to complete
w
e200z3 Power Architecture Core Reference Manual, Rev. 2
4 5 6
nonseq nonseq
addr z addr w
single single
data y
data z
okay okay okay
is taken because the second
z
7 8
idle
data w
okay
write
z
Freescale Semiconductor