Freescale Semiconductor e200z3 Reference Manual page 365

Table 9-12. Watchpoint Output Signal Assignments (continued)
Signal Name Type
1
jd_watchpt[5] DAC2 Data address compare 2 watchpoint. Set whenever a DAC2 compare occurs regardless of whether
DAC2 compares are enabled to set DBSR status.
j d_watchpt[6] DCNT1 Debug counter 1 watchpoint. Set whenever debug counter 1 decrements to zero regardless of
whether DCNT1 compares are enabled to set DBSR status.
jd_watchpt[7] DCNT2 Debug counter 2 watchpoint. Set whenever debug counter 2 decrements to zero regardless of
whether DCNT2 compares are enabled to set DBSR status.
1
If the corresponding event is completely disabled in DBCR0, either load-type or store-type data accesses are allowed to
generate watchpoints, otherwise watchpoints are generated only for the enabled conditions.
9.7 MMU and Cache Operation during Debug
Normal operation of the MMU may be modified during a debug session using the OnCE OCR. A debug
session begins when the CPU initially enters debug mode and ends when a OnCE command with Go+Exit
is executed, releasing the CPU for normal operation. If desired during a debug session, the debug firmware
may disable the translation process and may substitute default values for the access protection (UX, UR,
UW, SX, SR, SW) bits, and values obtained from the OnCE control register and page attribute (VLE, W,
I, M, G, E) bits normally provided by a matching TLB entry. In addition, no address translation is
performed; instead, a 1:1 mapping of effective-to-real addresses is performed.
When disabled during a debug session, TLB miss or TLB-related DSI conditions cannot occur. If the
debugger desires to use the normal translation process, the MMU may be left enabled in the OnCE OCR,
and normal translation (including the possibility of a TLB miss or DSI) remains in effect.
The OCRDMDIS, DW, DI, DM, DG, and DE control bits are used when debug mode is entered. Refer to
the bit definitions in the OCR (See
These substituted page attribute bits control cache operation on accesses initiated during debug. No
address translation is performed; instead, a 1:1 mapping between effective and real addresses is performed.
9.8 Enabling, Using, and Exiting External Debug Mode: Example
The following steps show one possible scenario for a debugger wishing to use the external debug facilities.
This simplified flow shows basic operations and does not cover all potential methods in depth.
Enable external debug mode and initialize debug registers:
1. To enable OnCE operation, the debugger should ensure that the jd_en_once is set.
2. Write a value to OCR in which OCR[DR] and OCR[WKUP] are set. The TAP controller must step
through the proper states as outlined earlier. This step places the CPU in a debug state where it is
halted and awaiting single-step commands or a release to normal mode.
3. Scan out the OSR value to determine that the CPU clock is running and the CPU has entered debug
state. This can be done in conjunction with a CPUSCR read. The OSR is shifted out during the
Shift-IR state. The CPUSCR is shifted out during the Shift-DR state. The debugger should save the
scanned-out value of CPUSCR for later restoration.
4. Select the DBCR0 register and update it with DBCR0[EDM] set.
Freescale Semiconductor
Section 9.5.5.3, "OnCE Control Register (OCR),"
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Debug Support
for more detail).
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