Freescale Semiconductor e200z3 Reference Manual page 38

e200z335 Core Complex Overview
General-Purpose Registers
0 31 32 63
1
(upper) GPR0 (lower)
GPR1
General-
GPR2 purpose
registers
• • •
GPR31
L1 Cache (Read-Only)
L1 cache
3
L1CFG0
spr 515
configuration
register 0
32 63
Interrupt vector
spr 63 IVPR
prefix register
spr 26 SRR0
Save/restore
registers 0/1
spr 27 SRR1
spr 58 CSRR0
Critical SRR 0/1
spr 59 CSRR1
3
spr 574
DSRR0
Debug interrupt
SRR 0/1
3
spr 575
DSRR1
Exception syndrome
ESR
spr 62
register
3 Machine check
spr 572 MCSR
syndrome register
Data exception
spr 61 DEAR
address register
Debug Registers
spr 308 DBCR0
spr 309 DBCR1
Debug control
registers 0–3
spr 310 DBCR2
spr 561 DBCR3
spr 304 DBSR
Debug status register
6
spr 562
DBCNT
Debug count register
spr 312 IAC1
Instruction address
spr 313 IAC2
compare
spr 314 IAC3
registers 1–4
spr 315 IAC4
Data address
spr 316 DAC1
compare
spr 317 DAC2
registers 1 and 2
spr 318 DVC1 Data value
compare
spr 319 DVC2 registers 1 and 2
1
The 64-bit GPR registers are accessed by the SPE as separate 32-bit registers by SPE instructions. Only SPE vector instructions can access the upper word.
2
USPRG0 is a separate physical register from SPRG0.
3
EIS–specific registers; not part of the Power ISA.
4
IVOR9 (handles auxiliary processor unavailable interrupt) is defined by the EIS but not supported by the e200z335.
1-6
User-Level Registers
Instruction-Accessible Registers
0 31 32
CR
spr 9 CTR
spr 8 LR
spr 1 XER
spr 512 SPEFSCR
3
ACC
Supervisor-Level Registers
Interrupt Registers
32
spr 400 IVOR0
spr 401 IVOR1
• • •
spr 415 IVOR15
spr 528 IVOR32
IVOR33
spr 529
spr 530 IVOR34
MMU Control and Status (Read/Write)
spr 1012 MMUCSR0
spr 624 MAS0
spr 625 MAS1
5
spr 626 MAS2
spr 627 MAS3
spr 628 MAS4
MAS6
spr 630
spr 48 PID0
MMU Control and Status (Read Only)
spr 1015 MMUCFG
spr 688 TLB0CFG
spr 689 TLB1CFG
Parallel Signature Unit Registers
dcr 272 PSCR
dcr 273 PSSR
dcr 274 PSHR
dcr 275 PSLR
dcr 276 PSCTR
dcr 277 PSUHR
dcr 278 PSULR
e200z3 Power Architecture Core Reference Manual, Rev. 2
63
Condition register spr 256 USPRG0
Count register
Link register spr 260
spr 261
Integer exception
register
spr 262
3 SP/embedded FP
spr 263
status/control register
Accumulator Time-Base Registers (Read-Only)
spr 268
spr 269
63
Interrupt vector offset
spr 1023
4
registers 0–15
spr 286
3
spr 287
3 Interrupt vector offset
registers 32–34
3
MMU control and status
3
register 0
spr 284
3
spr 285
3
3
spr 340
MMU assist registers
0–4 and 6
3
spr 336
3
3
Process ID
spr 1008
register 0
spr 1009
spr 1013
3
MMU configuration
spr 272–279
3
TLB configuration 0/1
3
6 spr 560
PS control
PS status
PS high
PS low
PS counter
PS update high
PS update low
User General SPR (Read/Write)
32 63
User SPR
2
general 0
General SPRs (Read-Only)
SPRG4
SPR general
SPRG5
registers 4–7
SPRG6
SPRG7
TBL
Time base
lower/upper
TBU
Configuration Registers
32 63
MSR
Machine state register
System version
3
SVR
register
PIR Processor ID register
Processor version
PVR
register
Timer/Decrementer Registers
spr 22 DEC Decrementer
Decrementer
spr 54 DECAR
auto-reload register
TBL
Time base
lower/upper
TBU
TCR Timer control register
TSR Timer status register
Miscellaneous Registers
3
HID0 Hardware
implementation
3
HID1
dependent 0–1
6 Branch control and
BUCSR
status register
SPRG0–7 General SPRs 0–7
Context Control (Read/Write)
Context control
6
CTXCR
register
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