Freescale Semiconductor e200z3 Reference Manual page 205

• Instruction from the illegal instruction class
• mtspr and mfspr instructions that specify an undefined SPR
• mtdcr and mfdcr instructions that specify an undefined DCR
The e200z3 invokes a privileged instruction program exception on attempted execution of the following
instructions when MSR[PR]=1 (user mode):
• A privileged instruction
• mtspr and mfspr instructions that specify an SPRN value with SPRN[5] = 1 (even if the SPR is
undefined).
The e200z3 invokes a trap exception on execution of tw and twi if the trap conditions are met and the
exception is not also enabled as a debug interrupt.
The e200z3 invokes an unimplemented operation program exception on attempted execution of the
instructions lswi, lswx, stswi, stswx, mfapidi, mfdcrx, mtdcrx, or any Book E floating-point instruction
when MSR[FP]=1. All other defined or allocated instructions that are not implemented by the e200z3
cause an illegal instruction program exception.
Table 4-16 lists register settings when a program interrupt is taken.
Register
SRR0 Set to the effective address of the excepting instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt.
MSR UCLE 0
SPE 0
WE 0
CE —
EE 0
ESR Illegal:
Privileged:
Trap:
Unimplemented:
MCSR Unchanged
DEAR Unchanged
Vector IVPR[32–47] || IVOR6[48–59] || 0b0000
4.6.8 Floating-Point Unavailable Interrupt (IVOR7)
The floating-point unavailable interrupt is implemented as defined in Book E. A floating-point unavailable
interrupt occurs when no higher priority exception exists, an attempt is made to execute a Book E-defined
floating-point instruction (including floating-point load, store, or move instructions), and the
floating-point available bit in the MSR is cleared (MSR[FP]=0).
Table 4-17 lists register settings when a floating-point unavailable interrupt is taken.
Freescale Semiconductor
Table 4-16. Program Interrupt Register Settings
Setting Description
PR 0
FP 0
ME —
FE0 0
PIL, [VLEMI]. All other bits cleared.
PPR, [VLEMI]. All other bits cleared.
PTR, [VLEMI]. All other bits cleared.
PUO, [FP], [VLEMI]. All other bits cleared.
e200z3 Power Architecture Core Reference Manual, Rev. 2
Interrupts and Exceptions
DE —
FE1 0
IS 0
DS 0
RI —
4-17