Freescale Semiconductor e200z3 Reference Manual page 164

Instruction Model
Opcode
Format
Extended
Primary
(Inst
(Inst )
21:31
0:5
X
011111 11000 01010 0
X
011111 11000 01010 1
X
011111 11000 10010 /
X
011111 11000 10110 /
X
011111 11000 11000 0
X
011111 11000 11000 1
X
011111 11001 11000 0
X
011111 11001 11000 1
X
011111 11010 10110 /
X
011111 11100 10010 ?
X
011111 11100 10110 /
X
011111 11100 11010 0
X
011111 11100 11010 1
X
011111 11101 10010 /
X
011111 11101 11010 0
X
011111 11101 11010 1
X
011111 11110 01011 0
X
011111 11110 01011 1
X
011111 11110 10010 /
X
011111 11110 10110 /
X
011111 11110 10111 /
X
011111 11111 01011 0
X
011111 11111 01011 1
X
011111 11111 10110 /
D
100000 ––––– ––––– –
D
100001 ––––– ––––– –
D
100010 ––––– ––––– –
D
100011 ––––– ––––– –
Legend:
- Don't care, usually part of an operand field
/ Reserved bit, invalid instruction form if encoded as 1
? Allocated for implementation-dependent use. See User' Manual for the implementation
3-36
Table 3-12. Instructions Sorted by Opcode (continued)
Mnemonic
)
addo Add and record OV
addo. Add and record OV and CR
tlbivax TLB Invalidate Virtual Address Indexed
lhbrx Load Halfword Byte-Reverse Indexed
sraw Shift Right Algebraic Word
sraw. Shift Right Algebraic Word and record CR
srawi Shift Right Algebraic Word Immediate
srawi. Shift Right Algebraic Word Immediate and record CR
mbar Memory Barrier
tlbsx TLB Search Indexed
sthbrx Store Halfword Byte-Reverse Indexed
extsh Extend Sign Halfword
extsh. Extend Sign Halfword and record CR
tlbre TLB Read Entry
extsb Extend Sign Byte
extsb. Extend Sign Byte and record CR
divwuo Divide Word Unsigned and record OV
divwuo. Divide Word Unsigned and record OV and CR
tlbwe TLB Write Entry
icbi Instruction Cache Block Invalidate
stfiwx Store Floating-Point as Int Word Indexed
divwo Divide Word and record OV
divwo. Divide Word and record OV and CR
dcbz Data Cache Block set to Zero
lwz Load Word and Zero
lwzu Load Word and Zero with Update
lbz Load Byte and Zero
lbzu Load Byte and Zero with Update
e200z3 Power Architecture Core Reference Manual, Rev. 2
Instruction
Freescale Semiconductor