Freescale Semiconductor e200z3 Reference Manual page 340

Debug Support
Event Name Type
Linked Instruction DAC1LNK,
Address and Data DAC2LNK
Address Compare
Event
Trap Debug Event TRAP
Branch Taken BRT
Debug Event
9-8
Table 9-2. Debug Event Descriptions (continued)
Data address compare debug events may be linked with an instruction address
compare event by setting the DAC1LNK and/or DAC2LNK control bits in DBCR2 to
further refine when a data address compare debug event is generated. DAC1 may be
linked with IAC1, and DAC2 (when not used as a mask or range bounds register) may
be linked with IAC3. When linked, a DAC1 (or DAC2) debug event occurs when the
same instruction that generates the DAC1 (or DAC2) hit also generates an IAC1 (or
IAC3) hit. When linked, the IAC1 (or IAC3) event is not recorded in the DBSR,
regardless of whether a corresponding DAC1 (or DAC2) event occurs, or whether the
IAC1 (or IAC3) event enable is set.
When enabled and execution of a load or store class instruction results in a data
access with an address, and that address meets the criteria specified in DBCR0,
DBCR2, DAC1, and DAC2, and the instruction also meets the criteria for generating
an instruction address compare event, a linked data address compare debug event
occurs. This event can occur and be recorded in DBSR regardless of the setting of
MSR[DE]. The normal DAC1 and DAC2 status bits in the DBSR are used for recording
these events. The IAC1 and IAC3 status bits are not set if the corresponding
instruction address compare register is linked.
Linking is enabled using DBCR2 control bits. If data address compare debug events
are used to control or modify operation of the debug counter, linking is also available,
even though DBCR0 may not have enabled IAC or DAC events. Also, instruction
address compare events that are linked may still affect the debug counter (if enabled
to) and may be used to either trigger a counter or be counted, in contrast to being
blocked from affecting the DBSR.
Note:
Linked DAC events are not recorded or counted if an lmw or stmw instruction is
interrupted before completion by a critical input or external input interrupt.
A trap debug event occurs if trap debug events are enabled (DBCR0[TRAP] = 1), a
trap instruction (tw, twi) is executed, and the conditions specified by the instruction for
the trap are met. This event can occur and be recorded in DBSR regardless of the
setting of MSR[DE]. When a trap debug event occurs, DBSR[TRAP] is set.
A branch taken debug event occurs if branch taken debug events are enabled
(DBCR0[BRT] = 1) and execution is attempted of a branch instruction that will be
taken (either an unconditional branch or a conditional branch whose branch condition
is true), and MSR[DE] = 1 or DBCR0[EDM] = 1. Branch taken debug events are not
recognized if MSR[DE] = 0 and DBCR0[EDM] = 0 at the time of execution of the
branch instruction and thus DBSR[IDE] can not be set by a branch taken debug event.
When a branch taken debug event is recognized, DBSR[BRT] is set to record the
debug exception, and the address of the branch instruction is recorded in DSRR0
(only when the interrupt is taken).
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Freescale Semiconductor