Freescale Semiconductor e200z3 Reference Manual page 261

Table 6-4. Timing for Integer Simple Instructions (continued)
6.7.1.2 SPE Load and Store Instruction Timing
Instruction timing for SPE load and store instructions is shown in
Actual timing depends on alignment; the table indicates timing for aligned operands.
Freescale Semiconductor
Instruction Latency Throughput
evrlwi 1
evrndw 1
evsel 1
evslw 1
evslwi 1
evsplatfi 1
evsplati 1
evsrwis 1
evsrwiu 1
evsrws 1
evsrwu 1
evsubfw 1
evsubifw 1
evxor 1
Table 6-5. SPE Load and Store Instruction Timing
Instruction Latency
evldd 1
evlddx 1
evldh 1
evldhx 1
evldw 1
evldwx 1
evlhhesplat 1
evlhhesplatx 1
evlhhossplat 1
evlhhossplatx 1
evlhhousplat 1
evlhhousplatx 1
evlwhe 1
e200z3 Power Architecture Core Reference Manual, Rev. 2
Instruction Pipeline and Execution Timing
Comments
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 6-4. The table is sorted by opcode.
Throughput Comments
1
1
1
1
1
1
1
1
1
1
1
1
1
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