Freescale Semiconductor e200z3 Reference Manual page 357

Table 9-10 describes the methods for entering debug mode.
Method Name
External debug Holding jd_de_b asserted while p_reset_b is asserted and holding it asserted following the negation of
request during p_reset_b causes the core to enter debug mode. After receiving an acknowledge through the OnCE status
reset register debug bit, the external command controller should negate jd_de_b before sending the first command.
Note that in this case the core does not execute an instruction before entering debug mode, although the first
instruction to be executed may be fetched before entering debug mode.
In this case, all values in the debug scan chain are undefined and the external debug control module is
responsible for proper initialization of the chain before debug mode is exited. In particular, the exception
processing associated with reset may not be performed when debug mode is exited; thus, the debug controller
must initialize PC, MSR, and IR to the image that the processor would have obtained in performing reset
exception processing, or it must cause the appropriate bit reset to be re-asserted.
Setting OCR[DR] while p_reset_b is asserted causes the device to enter debug mode; the chip may fetch the
Debug request
during reset first instruction of the reset interrupt handler but does not execute an instruction before entering debug mode.
In this case, all values in the debug scan chain are undefined and the external debug control module is
responsible for properly initializing the chain before debug mode is exited. In particular, interrupt processing
associated with reset may not be performed when debug mode is exited; thus, the debug controller must
initialize PC, MSR, and IR to the image that the processor would have obtained in performing reset exception
processing, or it must cause the appropriate reset to be re-asserted.
Debug request Setting OCR[DR] during normal chip activity causes the chip to finish execution of the current instruction and
during normal then enter debug mode. Note that in this case the chip completes execution of the current instruction and stops
activity after the newly fetched instruction enters the CPU instruction register. This process is the same for any newly
fetched instruction, including instructions fetched by the interrupt processing or those aborted by the interrupt
processing.
Debug request Setting OCR[DR] when the device is in the halted or stopped state ( p_halted or p_stopped set) causes the CPU
to exit the state and enter debug mode once the CPU clock m_clk has been restored. Note that in this case,
during halted or
stopped state the CPU negates both the p_halted and p_stopped outputs. Once the debug session has ended, the CPU
returns to the state it was in before entering debug mode.
To signal the chip-level clock generator to re-enable m_clk , the p_wakeup output is set whenever the debug
block is asserting a debug request to the CPU due to OCR[DR] being set, or jd_de_b assertion, and remains
set from then until the debug session ends ( jd_debug_b goes from set to negated). In addition, the status of
the jd_mclk_on input (after synchronization to the j_tclk clock domain) may be sampled along with other status
bits from the j_tdo output during the Shift-IR TAP controller state. This status may be used if necessary by
external debug firmware to ensure that proper scan sequences occur to registers in the m_clk clock domain.
Software Upon executing a 'bkpt' pseudo-instruction (for the core, defined to be an all zeros instruction opcode), when
request during OCR [FDB] is set (debug mode enable control bit is true) and DBCR0[EDM] = 1, the CPU enters debug mode
normal activity after the instruction following the 'bkpt' pseudo-instruction has entered the instruction register.
9.5.8 CPU Status and Control Scan Chain Register (CPUSCR)
A number of on-chip registers store the CPU pipeline status and are configured in a single scan chain for
access by the OnCE controller. CPUSCR contains these processor resources, which are used to restore the
pipeline and resume normal chip activity upon return from debug mode, as well as a mechanism for the
emulator software to access processor and memory contents.
pipeline information registers contained in the CPUSCR. Once debug mode has been entered, it is required
to scan in and update this register before exiting debug mode.
Freescale Semiconductor
Table 9-10. Methods for Entering Debug Mode
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Figure 9-8 shows the block diagram of the
Debug Support
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