Freescale Semiconductor e200z3 Reference Manual page 246

Instruction Pipeline and Execution Timing
Time Slot
First Inst.
Second Instruction
Third Instruction
6.3.4 Basic Load and Store Instruction Pipeline Operation
The EA calculations for load and store instructions are performed in the decode stage. The memory access
occurs in the execution stage.
If a load instruction is followed by a dependent ALU instruction, the load data is driven from the memory
in the MEM stage and feed-forwarded into the dependent ALU instruction in the following cycle. As a
result, there is no load-to-use pipeline bubble.
followed by a dependent add instruction.
Time Slot
First Load Instruction
Second Add Instruction
Figure 6-6. A Load Followed by a Dependent Add Instruction
Back-to-back load/store instructions are executed in a pipelined fashion, provided that their EA
calculations are not dependent on their previous load instructions.
for two back-to-back load instructions. In this case, the second load does not depend on its previous load
data for its EA calculation. Notice that the memory access of the first load instruction overlaps in time with
the EA calculation of the second load instruction.
6-8
IFETCH DECODE EXECUTE
IFETCH DECODE
Figure 6-5. Basic Pipeline Flow, Single-Cycle Instructions
Figure 6-6
IFETCH DEC/EA
IFETCH
e200z3 Power Architecture Core Reference Manual, Rev. 2
FFwd/WB
EXECUTE FFwd/WB
IFETCH DECODE EXECUTE
shows the instruction flow for a load instruction
MEM MEM
Feedforward
DECODE EXECUTE
Figure 6-7
FFwd/WB
MEM
shows the basic pipeline flow
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