Freescale Semiconductor e200z3 Reference Manual page 207

4.6.11 Decrementer Interrupt (IVOR10)
The e200z3 implements the decrementer exception as described in Book E. A decrementer interrupt
occurs when no higher priority exception exists, a decrementer exception condition exists (TSR[DIS]=1),
and the interrupt is enabled (both TCR[DIE] and MSR[EE]=1).
The timer status register (TSR) holds the decrementer interrupt bit set by the timer facility when an
exception is detected. The interrupt handler must clear this bit to avoid repeated decrementer interrupts.
Table 4-19 lists register settings when a decrementer interrupt is taken.
Register
SRR0 Set to the effective address of the instruction that the processor would have attempted to execute next
if no exception conditions were present.
SRR1 Set to the contents of the MSR at the time of the interrupt
MSR UCLE 0
SPE 0
WE 0
CE —
EE 0
ESR Unchanged
MCSR Unchanged
DEAR Unchanged
Vector IVPR[32–47] || IVOR10[48–59] || 0b0000
4.6.12 Fixed-Interval Timer Interrupt (IVOR11)
The e200z3 implements the fixed-interval timer exception as defined in Book E. The triggering of the
exception is caused by selected bits in the time base register changing from 0 to 1.
A fixed-interval timer interrupt occurs when no higher priority exception exists, a fixed-interval timer
exception exists (TSR[FIS]=1), and the interrupt is enabled (both TCR[FIE] and MSR[EE]=1).
The timer status register (TSR) holds the fixed-interval timer interrupt bit set by the timer facility when an
exception is detected. Software must clear this bit in the interrupt handler to avoid repeated fixed-interval
timer interrupts.
Table 4-20 lists register settings when a fixed-interval timer interrupt is taken.
Table 4-20. Fixed-Interval Timer Interrupt Register Settings
Register
SRR0 Set to the effective address of the instruction that the processor would have attempted to execute next if no exception
conditions were present.
SRR1 Set to the contents of the MSR at the time of the interrupt.
Freescale Semiconductor
Table 4-19. Decrementer Interrupt Register Settings
Setting Description
PR 0
FP 0
ME —
FE0 0
Setting Description
e200z3 Power Architecture Core Reference Manual, Rev. 2
Interrupts and Exceptions
DE —
FE1 0
IS 0
DS 0
RI —
4-19