Freescale Semiconductor e200z3 Reference Manual page 401

MCKO
MSEO_B
MDO[1:0]
00 11 00 00 00 11 10 11 00 11 10 10 11
Figure 10-31. Program Trace—Indirect Branch with Synchronization Message
10.8 Data Trace
This section deals with the data trace mechanism supported by the Nexus3/Nexus2+ module. Data trace is
implemented by means of data write messaging (DWM) and data read messaging (DRM) in accordance
with the IEEE-ISTO 5001-2003 standard.
10.8.1 Data Trace Messaging (DTM)
Data trace messaging for the e200z3 is accomplished by snooping the e200z3 virtual data bus between the
CPU and MMU, and storing the information for qualifying access, based on enabled features and matching
target addresses. The Nexus3/Nexus2+ module traces all data accesses that meet the selected range and
attributes.
Data trace is only performed on the e200z3 virtual data bus. This allows for
data visibility for e200z3 processors that incorporate a data cache. Only
e200z3 CPU-initiated accesses are traced. No DMA accesses to the AHB
system bus are traced.
Data trace messaging can be enabled in one of two ways:
• Setting DC1[TM] to enable data trace.
• Using WT[DTS] to enable data trace on watchpoint hits. e200z3 watchpoints are configured within
the Nexus1 module.
10.8.2 DTM Message Formats
The Nexus3/Nexus2+ block supports five types of DTM messages: data write, data read, data write
synchronization, data read synchronization, and error messages.
10.8.2.1 Data Write Messages
The data write message contains the data write value and the address of the write access, relative to the
previous data trace message. Data write message information is messaged out in the format shown in
Figure 10-32:
Freescale Semiconductor
TCODE = 12
Source processor = 0000
Number of sequential instructions = 3
Full target address = 0xDEADFACE
e200z3 Power Architecture Core Reference Manual, Rev. 2
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NOTE
Nexus3/Nexus2+ Module
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