Freescale Semiconductor e200z3 Reference Manual page 200

Interrupts and Exceptions
Register
CSRR0 On a best-effort basis, the e200z3 sets this to the address of some instruction that was executing or about
to be executing when the machine check condition occurred.
CSRR1 Set to the contents of the MSR at the time of the interrupt
MSR UCLE 0
SPE 0
WE 0
CE 0
ESR Unchanged
MCSR Updated to reflect the sources of a machine check
DEAR Unchanged unless machine check is due to a data access causing a cache parity error to be signaled;
updated with data access effective address in that case
Vector IVPR[32–47] || IVOR1[48–59] || 0b0000
1
Cleared when the debug APU is disabled. Clearing of DE is optionally supported by control in HID0 when the debug
APU is enabled.
2
RI is cleared by all critical class interrupts using CSRR0/1 and the machine check interrupt. These interrupt
handlers should set RI early in the handler after CSRR0/1 have been saved to allow for improved recoverability.
The machine check input, p_mcp_b, can be masked by HID0[EMCP].
Most machine check exceptions are unrecoverable in the sense that execution cannot resume in the context
that existed before the interrupt. However, system software can use the machine check interrupt handler to
try to identify and recover from the machine check condition. In particular, the MCSR is provided to
identify the sources of a machine check and may be used to identify recoverable events.
The interrupt handler should set MSR[ME] as early as possible to avoid entering checkstop state if another
machine check condition occurs.
4.6.2.2 Checkstop State
The following exception conditions can cause a checkstop if MSR[ME]=0:
• A machine check occurs (other than a non-maskable interrupt).
• First instruction in an interrupt handler cannot be executed due to a translation miss (ITLB), a page
marked no execute (ISI), or a bus error termination.
• Bus error termination for a buffered store .
• Precise external termination error occurs and MSR[EE]=0.
Non-exception–related checkstop conditions are as follows:
• TCR[WRC]—Watchdog reset control bits set to checkstop on second watchdog timer overflow
event
4-12
Table 4-10. Machine Check Interrupt Register Settings
Setting Description
EE 0
PR 0
FP 0
ME 0
e200z3 Power Architecture Core Reference Manual, Rev. 2
1
DE 0
FE1 0
IS 0
DS 0
2
RI 0
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