Freescale Semiconductor e200z3 Reference Manual page 190

Interrupts and Exceptions
The following terms are used to describe the stages of exception processing:
Recognition Exception recognition occurs when the condition that can cause an exception is
identified by the processor. Recognition is also referred to as an 'exception event.'
Taken An interrupt is said to be taken when control of instruction execution is passed to
the interrupt handler; that is, the context is saved, the instruction at the appropriate
vector offset is fetched, and the interrupt handler routine begins.
Handling Interrupt handling is performed by the software linked to the appropriate vector
offset. Interrupt handling is begun in supervisor mode.
Returning from an interrupt is performed by executing the appropriate return from interrupt instruction
(rfi, rfci, or rfdi), which restores state information from their respective save/restore registers and returns
instruction fetching to the interrupted flow.
4.2 e200z3 Interrupts
The Book E architecture specifies that interrupts can be precise or imprecise, synchronous or
asynchronous, and critical or non-critical. These characteristics are described as follows:
• Asynchronous exceptions are caused by events external to the processor's instruction execution.
• Synchronous exceptions are directly caused by instructions or by an event somehow synchronous
to the program flow, such as a context switch.
• A precise interrupt architecturally guarantees that no instruction beyond the instruction causing the
exception has (visibly) executed. An imprecise interrupt does not have this guarantee.
• Book E defines critical and non-critical interrupt types, and the e200z3 defines an
implementation-specific debug APU that includes the debug interrupt type. Each interrupt type
provides separate resources (save/restore registers and return from interrupt instructions) that allow
interrupts of one type to not interfere with the state handling of an interrupt of another type.
Table 4-1 describes how these definitions apply to the interrupts implemented by the e200z3 core.
Interrupt Types
System reset
Machine check
Critical input
Watchdog timer
External input
Fixed-interval timer
Decrementer
Instruction-based debug
Debug (UDE)
Debug imprecise
Data storage/alignment/TLB
Instruction storage/TLB
4-2
Table 4-1. Interrupt Classifications
Synchronous/Asynchronous Precise/Imprecise Critical/Non-Critical/Debug
Asynchronous, non-maskable
—
Asynchronous, maskable
Asynchronous, maskable
Synchronous
Asynchronous
Synchronous
e200z3 Power Architecture Core Reference Manual, Rev. 2
Imprecise
— Critical
Imprecise Critical
Imprecise Non-critical
Precise Critical/debug
Imprecise Critical/debug
Precise Non-critical
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