Freescale Semiconductor e200z3 Reference Manual page 286

External Core Complex Interfaces
Signal I/O
p_avec_b I Autovector. Determines how a vector is chosen for critical and external interrupt signals.
State
Meaning
Timing Must be driven to a valid state during each clock cycle that either p_extint_b or p_critint_b is
p_voffset[0:15 I Interrupt vector offset. Vector offset and context selector used when processing begins for an incoming
]
interrupt request. Ignored if multiple hardware contexts are not implemented.
State
Meaning
Timing Sampled with the p_extint_b and p_critint_b interrupt request inputs; must be driven to a valid
p_iack O Interrupt vector acknowledge. Interrupt vector acknowledge indicator to allow external interrupt controllers
to be informed when a critical input or external input interrupt is being processed.
State
Meaning
Timing Assertion—Asserted after the cycle in which p_avec_b and p_voffset[0:15] are sampled in
p_mcp_b I Machine check. Machine check interrupt request to the core. Masked by HID0[EMCP].
State
Meaning
Timing Because this signal is not internally synchronized by the core, it must meet setup and hold time
Table 7-12 describes the timer facility signals, which are associated with the time base, watchdog,
fixed-interval, and decrementer facilities.
7-18
Table 7-11. Descriptions of Interrupt Signals (continued)
Asserted—Asserted with either the p_extint_b or p_critint_b interrupt request to request use of
the IVOR4 or IVOR0 for obtaining an exception vector offset.
Negated—If negated when a p_extint_b or p_critint_b interrupt is requested, an external vector
offset and context selector is taken from p_voffset[0:15] .
asserted.
Assertion—Level-sensitive, must remain asserted to have guaranteed recognition.
Correspond to IVOR n [16–31]. p_voffset[0:11] are used in forming the exception handler
address; p_voffset[12:15] are used to select a new operating context when multiple hardware
contexts are implemented.
value when either signal is asserted unless p_avec_b is also asserted. If p_avec_b is asserted,
these inputs are not used.
Assertion—Level-sensitive; must remain asserted to guarantee correct recognition. Must be
asserted concurrently with p_extint_b and p_critint_b when used.
Asserted—An interrupt vector is being acknowledged.
Negated—An interrupt vector is not being acknowledged.
preparation for exception processing. See
diagrams.
Asserted—A machine check interrupt is being requested.
Negated—A machine check interrupt is not being requested.
constraints to m_clk when the core clock is running. p_mcp_b is not sampled while the core is
in the halted or stopped power management states.
Assertion— p_mcp_b is sampled on two consecutive m_clk periods to detect a transition from
the negated to the asserted state. It is internally qualified with this transition, but must
remain asserted to be guaranteed to be recognized
e200z3 Power Architecture Core Reference Manual, Rev. 2
Signal Description
Figure 7-32 and
.
Figure 7-33 for timing
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