Freescale Semiconductor e200z3 Reference Manual page 241

6.1.3 Branch Unit
The branch unit contains an eight-entry branch target buffer (BTB) to accelerate execution of branch
instructions.
Untaken conditional branches execute in a single clock. Branches with successful target prefetching have
an effective execution time of one clock cycle. All other taken branches have an execution time of two
clocks.
6.1.4 Instruction Decode Unit
The decode unit includes the instruction buffers. A single instruction can be decoded each cycle. The major
functions of the decode logic are as follows:
• Opcode decoding to determine the instruction class and resource requirements for each instruction
being decoded.
• Source and destination register dependency checking.
• Execution unit assignment.
• Determine any decode serializations and inhibit subsequent instruction decoding.
The decode unit operates in a single processor clock cycle.
6.1.5 Exception Handling
The exception handling unit includes logic to handle exceptions, interrupts, and traps.
6.2 Execution Units
The core data execution units consist of the integer unit and the load/store unit. Included in the execution
units section are the general purpose registers (GPRs). Instructions with data dependencies begin
execution when all such dependencies are resolved.
6.2.1 Integer Execution Unit
The integer execution unit is used to process arithmetic and logical instructions. Adds, subtracts,
compares, count leading zeros, shifts, and rotates execute in a single cycle.
Multiply instructions have a latency and throughput rate of 1 cycle.
Divide instructions have a variable latency (6–16 cycles) depending on the operand data. The worst case
integer divide requires 16 cycles. While the divide is running, the rest of the pipeline is unavailable for
additional instructions (blocking divide).
6.2.2 Load/Store Unit
The load/store unit executes instructions that move data between the GPRs and the memory subsystem. A
load followed by a dependent instruction does not incur any pipeline stall, except when the dependent
Freescale Semiconductor
e200z3 Power Architecture Core Reference Manual, Rev. 2
Instruction Pipeline and Execution Timing
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