Freescale Semiconductor e200z3 Reference Manual page 309

m_clk
p_htrans
p_addr,p_hprot
p_hsize ,
p_hbstrb , etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
The first portion of the misaligned write transfer starts in C1. During C1, the core places valid values on
the address bus and transfer attributes. The p_[d,i]_hwrite signal is driven high for a write cycle. The
transfer size attribute (p_[d,i]_hsize) indicates the size of the transfer. Even though the transfer is
misaligned, the size value driven corresponds to the size of the entire misaligned data item.
p_[d,i]_hunalign is driven high to indicate that the access is misaligned. The p_[d,i]_hbstrb outputs are
asserted to indicate the active byte lanes for the write, which may not correspond to size and low-order
address outputs. p_[d,i]_htrans is driven to NONSEQ.
During C2, data for addr
attribute values that were driven during C1 to enable writing of one or more bytes of memory.
The second portion of the misaligned write transfer request is made during C2 to addr
to the next higher 64-bit boundary), and because the first portion of the misaligned access is completing,
it is taken at the end of C2. The p_[d,i]_htrans signals indicate NONSEQ. The size value driven is the size
of the remaining bytes of data in the misaligned write, rounded up (for the 3-byte case) to the next higher
power-of-2. The p_[d,i]_hbstrb signals indicate the active byte lanes. For the second portion of a
misaligned transfer, p_[d,i]_hunalign is driven high for the 3-byte case (low for all others).
The next write access is requested in C3 and p_[d,i]_htrans indicates NONSEQ. p_[d,i]_hunalign is
negated, because this access is aligned.
An example of a misaligned write cycle followed by an aligned read cycle is shown in
similar to the example in
Freescale Semiconductor
1 2
nonseq
addr x addr x+
single single
data x
okay
Figure 7-12. Misaligned Write, Write, Full Pipelining
is driven, and the addr
x x
Figure 7-12.
e200z3 Power Architecture Core Reference Manual, Rev. 2
3
nonseq nonseq
addr y
single
**
data x+
okay okay
memory access takes place using the address and
External Core Complex Interfaces
4 5
idle
data y
okay
(which is aligned
x+
Figure 7-13. It is
7-41