Freescale Semiconductor e200z3 Reference Manual page 381

10.4.4 Development Status Register (DS)
The development status registe shown in
mode is entered or exited, or an SOC- or e200z3-defined low-power mode is entered, a debug status
message is transmitted with DS[31–25]. The external tool can read this register at any time.
31 30
Field DBG LPC
Reset
R/W
Number
Bits
31
30–28
27–26
25
24–0
10.4.5 Read/Write Access Control/Status Register (RWCS)
The read write access control/status register, shown in
Read/write access provides DMA-like access to memory-mapped resources on the AHB system bus either
while the processor is halted, or during runtime. RWCS also provides read/write access status information;
see Table 10-14.
Freescale Semiconductor
Figure 10-7
28 27 26 25 24
LPC CHK
Figure 10-7. Development Status Register (DS)
Table 10-12. DS Field Descriptions
Name
DBG e200z3 CPU debug mode status
0 CPU not in debug mode
1 CPU in debug mode ( jd_debug_b signal asserted)
LPS e200z3 system low power mode status
000 Normal (run) mode
XX1 Doze mode ( p_doze signal asserted)
X1X Nap mode ( p_nap signal asserted)
1XX Sleep mode ( p_sleep signal asserted)
LPC e200z3 CPU low power mode status
00 Normal (run) mode
01 CPU in halted state ( p_halted signal asserted)
10 CPU in stopped state ( p_stopped signal asserted)
11 CPU in Waiting state (p_waiting signal asserted)
CHK e200z3 CPU checkstop status
0 CPU not in checkstop state
1 CPU in checkstop state ( p_chkstop signal asserted)
— Reserved, should be cleared.
e200z3 Power Architecture Core Reference Manual, Rev. 2
is used to report system debug status. When debug
—
All zeros
Read–only
0x4
Description
Figure 10-8, provides control for read/write access.
Nexus3/Nexus2+ Module
0
10-15