Freescale Semiconductor e200z3 Reference Manual page 23

Table
Number
4-24 Debug Exceptions ................................................................................................................. 4-22
4-25 Debug Interrupt Register Settings......................................................................................... 4-23
4-26 TSR Watchdog Timer Reset Status ....................................................................................... 4-26
4-27 DBSR Most Recent Reset ..................................................................................................... 4-26
4-28 System Reset Register Settings............................................................................................. 4-26
4-29 SPE Unavailable Interrupt Register Settings ........................................................................ 4-26
4-30 SPE Floating-Point Data Interrupt Register Settings............................................................ 4-27
4-31 SPE Floating-Point Round Interrupt Register Settings......................................................... 4-28
4-32 e200z3 Exception Priorities .................................................................................................. 4-29
4-33 MSR Setting Due to Interrupt ............................................................................................... 4-32
5-1 TLB Maintenance Programming Model ................................................................................. 5-2
5-2 Page Size (for e200z3 Core) and EPN Field Comparison ...................................................... 5-5
5-3 TLB Entry Bit Fields for e200z3 ............................................................................................ 5-9
5-4 tlbivax EA Bit Definitions .................................................................................................... 5-11
5-5 TLB Entry 0 Values after Reset ............................................................................................ 5-13
5-6 MMU Assist Register Field Updates .................................................................................... 5-15
6-1 Pipeline Stages ........................................................................................................................ 6-4
6-2 Instruction Class Cycle Counts ............................................................................................. 6-17
6-3 Instruction Timing by Mnemonic ......................................................................................... 6-17
6-4 Timing for Integer Simple Instructions................................................................................. 6-22
6-5 SPE Load and Store Instruction Timing ............................................................................... 6-23
6-6 SPE Complex Integer Instruction Timing............................................................................. 6-24
6-7 SPE Vector Floating-Point Instruction Timing ..................................................................... 6-28
6-8 Scalar SPE Floating-Point Instruction Timing...................................................................... 6-29
6-9 Performance Effects of Storage Operand Placement ............................................................ 6-30
7-1 Interface Signal Definitions .................................................................................................... 7-4
7-2 Processor Clock Signal Description........................................................................................ 7-7
7-3 Descriptions of Signals Related to Reset ................................................................................ 7-8
7-4 Descriptions of Signals for the Address and Data Buses........................................................ 7-9
7-5 Descriptions of Transfer Attribute Signals ............................................................................. 7-9
7-6 Descriptions of Signals for Byte Lane Specification ............................................................ 7-11
7-7 Byte Strobe Assertion for Transfers...................................................................................... 7-11
7-8 Big-and Little-Endian Storage (64-Bit GPR Contains 'A B C D E F G H') ........................ 7-13
7-9 Descriptions of Signals for Transfer Control Signals ........................................................... 7-16
7-10 Descriptions of Master ID Configuration Signals................................................................. 7-17
7-11 Descriptions of Interrupt Signals .......................................................................................... 7-17
7-12 Descriptions of Timer Facility Signals ................................................................................. 7-19
7-13 Descriptions of Processor Reservation Signals..................................................................... 7-19
7-14 Descriptions of Miscellaneous Processor Signals................................................................. 7-19
7-15 Descriptions of Processor State Signals................................................................................ 7-20
7-16 Descriptions of Power Management Control Signals ........................................................... 7-21
Freescale Semiconductor
Tables
Title
e200z3 Power Architecture Core Reference Manual, Rev. 2
Page
Number
3