Freescale Semiconductor e200z3 Reference Manual page 311

7.5.2 Burst Accesses
Figure 7-14 shows functional timing for a burst read transfer.
m_clk
p_htrans
p_addr,p_hprot
p_hsize,
p_hbstrb, etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
The p_[d,i]_hburst signals indicate INCR for all burst transfers. The p_[d,i]_hunalign signal is negated.
p_[d,i]_hsize indicates 64-bits, and all eight p_[d,i]_hbstrb signals are asserted. The burst address is
aligned to a 64-bit boundary and increments by double words. Note that in this example four beats are
shown, but in operation the burst may be of any length including only a single beat.
Bursts can be interrupted immediately at any time and can be followed by
any type of cycle. No idle cycle is required.
Freescale Semiconductor
1 2
nonseq seq
addr x addr x+8
data x
okay okay
Figure 7-14. Burst Read Transfer
NOTE
e200z3 Power Architecture Core Reference Manual, Rev. 2
Burst Read
3 4
seq seq
addr x+16 addr x+24
INCR
data x+8 data x+16
okay okay
External Core Complex Interfaces
5 6
...
data x+24
okay
7-43