Freescale Semiconductor e200z3 Reference Manual page 151

Opcode
Format
Primary Extended
(Inst ) (Inst
0:5 21:31
A
111111 ––––– 10100 0
A
111111 ––––– 10100 1
A
111011 ––––– 10100 0
A
111011 ––––– 10100 1
X 011111 11110 10110 /
X 011111 00000 10110 /
X 011111 ––––– 01111 /
XL 010011 00100 10110 /
D 100010 ––––– ––––– –
D 100011 ––––– ––––– –
X 011111 00011 10111 /
X 011111 00010 10111 /
D
110010 ––––– ––––– –
D
110011 ––––– ––––– –
X
011111 10011 10111 /
X
011111 10010 10111 /
D
110000 ––––– ––––– –
D
110001 ––––– ––––– –
X
011111 10001 10111 /
X
011111 10000 10111 /
D 101010 ––––– ––––– –
D 101011 ––––– ––––– –
X 011111 01011 10111 /
X 011111 01010 10111 /
X 011111 11000 10110 /
D 101000 ––––– ––––– –
D 101001 ––––– ––––– –
X 011111 01001 10111 /
Legend:
- Don't care, usually part of an operand field
/ Reserved bit, invalid instruction form if encoded as 1
? Allocated for implementation-dependent use.
Freescale Semiconductor
Table 3-11. Instructions Sorted by Mnemonic (continued)
Mnemonic
)
1
fsub Floating Subtract
1
fsub. Floating Subtract and record CR
1
fsubs Floating Subtract Single
1
fsubs. Floating Subtract Single and record CR
icbi Instruction Cache Block Invalidate
icbt Instruction Cache Block Touch
2
isel Integer Select
isync Instruction Synchronize
lbz Load Byte and Zero
lbzu Load Byte and Zero with Update
lbzux Load Byte and Zero with Update Indexed
lbzx Load Byte and Zero Indexed
1
lfd Load Floating-Point Double
1
lfdu Load Floating-Point Double with Update
1
lfdux Load Floating-Point Double with Update Indexed
1
lfdx Load Floating-Point Double Indexed
1
lfs Load Floating-Point Single
1
lfsu Load Floating-Point Single with Update
1
lfsux Load Floating-Point Single with Update Indexed
1
lfsx Load Floating-Point Single Indexed
lha Load Half Word Algebraic
lhau Load Half Word Algebraic with Update
lhaux Load Half Word Algebraic with Update Indexed
lhax Load Half Word Algebraic Indexed
lhbrx Load Half Word Byte-Reverse Indexed
lhz Load Half Word and Zero
lhzu Load Half Word and Zero with Update
lhzux Load Half Word and Zero with Update Indexed
e200z3 Power Architecture Core Reference Manual, Rev. 2
Instruction Model
Instruction
3-23