Freescale Semiconductor e200z3 Reference Manual page 240

Instruction Pipeline and Execution Timing
OnCE/Nexus
Control Logic
Memory
Management
Address
32
Data
64
Control
N
6.1.1 Control Unit
The control unit coordinates the instruction fetch unit, branch unit, instruction decode unit, instruction
issue unit, completion unit, and exception handling logic.
6.1.2 Instruction Unit
The instruction unit controls the flow of instructions to the instruction buffers and decode unit. Six prefetch
buffers allow the instruction unit to fetch instructions ahead of actual execution, and serve to decouple
memory and the execution pipeline.
6-2
CPU
Control Logic
LR
Unit CR
SPR
CTR
XER
Instruction Unit
Instruction Buffer
PC
Unit
Load/
Store
Unit
Data Bus Interface Unit
32
Address Data
Figure 6-1. e200z3 Block Diagram
e200z3 Power Architecture Core Reference Manual, Rev. 2
GPR
(mtspr/mfspr)
Branch
Unit
64 N
Control
Integer
Execution
Unit
Multiply
Unit
Control
External
SPR
Data
Interface
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