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STER—Self-Test Error Register
Address
BB + 0000 1900
Access
R/W
The STER register contains address information pertaining to data
mismatch failures while self-test executes in POEM (pause on er-
ror) mode. The contents of this register when read after an error
has been detected in POEM mode can be used to isolate the failing
DRAM string and to indicate which of the four MDIs the error was
detected in. This information in conjunction with the four ST-
DERA:E registers located in the MDI ASICs can be used to isolate
down to a failing DRAM bit or bits. This register is cleared when
MDRA<POEMC> is asserted.
31
RSVD
STE3
STE2
STE1
STE0
RSVD
8
7
6
5
4
3
2
0
FSTR
BXB-0750-93
System Registers 7-95
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