Mdi Error Detection And Correction Logic; Error Conditions Monitored By The Mdis - DEC AlphaServer 8200 Technical Manual

on all CSR reads from memory. The ECC bits are generated across bits
<63:0> and transmitted on TLSB_ECC<7:0>.

5.2.4 MDI Error Detection and Correction Logic

The four MDIs monitor the data received from the TLSB for write data er-
rors. They also monitor read data for ECC errors after it has been trans-
mitted onto the TLSB. Table 5-5 summarizes the errors detected by each
of the four MDIs.
Table 5-5

Error Conditions Monitored by the MDIs

5-12 Memory Interface
Error CSR
TLESRn<21>
CRECC
TLESRn<20>
CWECC
UECC TLESRn<19>
TLESRn<17>
TCE
TLESRn<16>
TDE
TLESRn<15:8>
SYND1
TLESRn<7:0>
SYND0
• Correctable Read ECC Error
This bit is asserted when a correctable ECC error is detected during
memory read data cycles.
• Correctable Write ECC Error
This bit is asserted when a correctable ECC error is detected during
memory write data cycles.
• Uncorrectable ECC Error
This bit is asserted when an uncorrectable ECC error is detected dur-
ing any memory data cycle.
• Transmit Check Error
Each TLSB node is required to compare the data that it transmitted
onto the TLSB when it is the selected transmitter with the data that
actually appeared on the bus. This check is accomplished by storing
the data just prior to driving it onto the TLSB and comparing it with
the data received in the bus receiver latches on the next clock tick.
Each MDI performs the comparison on its quadword of TLSB data. If
the data in the receiver latches does not match that transmitted, the
Transmit Check Error bit in that MDI's Bus Error Syndrome Register
is asserted.
• Transmitter During Error
This bit is asserted when an ECC error is detected during bus cycles
when this node was the source of the TLSB data.
• Syndrome1
When an ECC error is detected in data word 1, the syndrome is latched
in these bits. This field is undefined when either CRECC, CWECC, or
UECC is zero.
• Syndrome0
When an ECC error is detected in data word 0, the syndrome is latched
Description
Correctable read ECC error
Correctable write ECC error
Uncorrectable ECC error
Data transmit check error
Data transmitter during error
Data 1 error syndromes
Data 0 error syndromes