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DEC AlphaServer 8400 Technical Manual

DEC AlphaServer 8400 Technical Manual (383 pages)

Brand: DEC | Category: Server | Size: 0 MB

Table of Contents

Table of Contents
3
Preface

15
- Digital Alphaserver 8200/8400 Documentation
  17
- Related Documents
  19
Chapter 1 Overview

21
- Configuration
  21
- Bus Architecture
  22
  - Alphaserver 8400 System Block Diagram
    22
- CPU Module
  23
- Decchip 21164
  23
- Backup Cache
  24
- TLSB Interface
  24
- Console Support Hardware
  24
- Memory Module
  24
- I/O Architecture
  25
- Software
  26
- Console
  26
- Openvms Alpha
  27
- Digital UNIX
  27
- Diagnostics
  27
- ROM-Based Diagnostics
  27
- Loadable Diagnostic Execution Environment
  28
- Online Exercisers
  28
Chapter 2 TLSB Bus

29
- Overview
  29
- Transactions
  30
- Arbitration
  30
- Cache Coherency Protocol
  30
- Error Handling
  30
- TLSB Signal List
  31
- TLSB Bus Signals
  31
- Operation
  33
- Physical Node ID
  33
- TLSB Physical Node Identification
  33
- Virtual Node Identification
  34
- Address Bus Concepts
  34
  - TLSB Memory Address Bit Mapping
    35
- Memory Bank Addressing Scheme
  36
- CSR Addressing Scheme
  36
- Memory Bank Address Decoding
  37
- Interleave Field Values for Two-Bank Memory Modules
  37
  - Address Decode
    38
- Bank Available Status
  39
- Address Bus Sequencing
  39
- Address Bus Arbitration
  40
- Initiating Transactions
  40
- Distributed Arbitration
  40
- Address Bus Transactions
  40
- Module Transactions
  40
- Address Bus Priority
  40
- Address Bus Request
  41
- Asserting Request
  41
- Early Arbitration
  41
- False Arbitration Effect on Priority
  42
- Look-Back-Two
  42
- Bank Available Transition
  42
- Bank Collision
  43
- Bank Lock and Unlock
  43
- CSR Bank Contention
  43
- Command Acknowledge
  44
- Arbitration Suppress
  44
- Address Bus Cycles
  44
- Address Bus Commands
  45
  - TLSB Address Bus Commands
    45
- Data Bus Concepts
  46
- Data Bus Sequencing
  46
- Hold
  46
- Back-To-Back Return Data
  47
- Back-To-Back Return with HOLD
  47
- CSR Data Sequencing
  47
- Data Bus Functions
  47
- Data Return Format
  47
- Sequence Numbers
  48
- Sequence Number Errors
  48
- Data Field
  48
- Data Wrapping
  48
- ECC Coding
  49
  - 64-Bit ECC Coding Scheme
    49
  - TLSB Data Wrapping
    49
- ECC Error Handling
  50
- Tlsb_Data_Valid
  50
- Tlsb_Shared
  50
- Tlsb_Dirty
  51
- Tlsb_Statchk
  51
- Miscellaneous Bus Signals
  52
- CSR Addressing
  53
- CSR Address Space Regions
  54
  - TLSB CSR Address Bit Mapping
    54
  - TLSB CSR Space Map
    55
- TLSB Node Base Addresses
  56
- TLSB CSR Address Mapping
  57
- TLSB Mailboxes
  58
  - Mailbox Data Structure
    58
- Window Space I/O
  60
- CSR Write Transactions to Remote I/O Window Space
  60
- CSR Read Transactions to Remote I/O Window Space
  60
- TLSB Errors
  61
- Error Categories
  62
- Hardware Recovered Soft Errors
  62
- Software Recovered Soft Errors
  62
- Hard Errors
  62
- System Fatal Errors
  62
- Error Signals
  63
- Address Bus Errors
  63
- Transmit Check Errors
  63
- Command Field Parity Errors
  64
- No Acknowledge Errors
  64
- Unexpected Acknowledge
  65
- Bank Lock Error
  65
- Bank Available Violation Error
  65
- Memory Mapping Register Error
  66
  - Multiple Address Bus Errors
    66
  - Summary of Address Bus Errors
    66
  - Data Bus Errors
    67
- Address Bus Error Summary
  67
- Signals Covered by Tlesrn Registers
  67
  - Single-Bit ECC Errors
    68
  - Double-Bit ECC Errors
    68
  - Illegal Sequence Errors
    68
  - SEND_DATA Timeout Errors
    68
  - Data Status Errors
    69
  - Transmit Check Errors
    69
  - Multiple Data Bus Errors
    69
  - Summary of Data Bus Errors
    70
  - Additional Status
    70
- Data Bus Error Summary
  70
  - Error Recovery
    71
  - Read Errors
    71
  - Write Errors
    73
Chapter 3 CPU Module

75
- Major Components
  75
- Decchip 21164 Processor
  76
  - CPU Module Simple Block Diagram
    76
- Mmg
  77
- Adg
  77
- Diga
  77
- B-Cache
  78
- Console
  78
- Serial ROM Port
  79
- Directly Addressable Console Hardware
  79
- CPU Module Address Space
  80
- Directly Addressable Console Hardware
  80
  - Memory Space
    81
  - I/O Space
    82
  - I/O Window Space
    82
  - TLSB CSR Space
    82
    
    TLSB CSR Space Map
    82
  - Gbus Space
    83
  - CPU Module Window Space Support
    84
  - Window Space Reads
    84
  - Window Space Writes
    84
  - Flow Control
    84
  - PCI Accesses
    85
- Decrement Queue Counter Address Assignments
  85
  - Sparse Space Reads and Writes
    86
  - Dense Space Reads and Writes
    87
- Valid Values for Address Bits <6:5
  87
  - CPU Module Errors
    88
  - Error Categories
    88
  - Soft Errors
    88
  - Hard Errors
    88
  - Faults
    89
  - Nonacknowledged CSR Reads
    90
  - Address Bus Errors
    90
  - Transmit Check Errors
    91
  - Command Field Parity Errors
    91
  - No Acknowledge Errors
    92
  - Unexpected Acknowledge Error
    92
  - Memory Mapping Register Error
    92
  - Data Bus Errors
    92
  - Multiple Errors
    93
Chapter 4 Memory Subsystem

95
- Internal Cache
  95
- Instruction Cache
  95
- Data Cache
  95
- Second-Level Cache
  96
- Backup Cache
  96
- Cache Coherency
  96
- B-Cache Tags
  97
  - Cache Index and Tag Mapping to Block Address (4MB)
    97
  - Cache Index and Tag Mapping to Block Address (1MB)
    97
- Updates and Invalidates
  98
- Duplicate Tags
  98
- B-Cache States
  98
- B-Cache State Changes
  99
- Victim Buffers
  100
- Lock Registers
  100
- State Transition Due to TLSB Activity
  100
- State Transition Due to Processor Activity
  101
  - Cache Coherency on Processor Writes
    102
- CPU Module Response to Lock Register and Victim Buffer Address Hits
  102
  - Memory Barriers
    103
  - Main Memory
    103
  - Major Sections
    104
- Memory Module Block Diagram
  104
  - Control Address Interface
    105
  - Memory Data Interface
    105
  - DRAM Arrays
    106
  - Memory Organization
    107
- Memory Array Capacity
  107
- Two-Way Interleave of a 128-Mbyte DRAM Array
  108
- Interleaving Different Size Memory Modules
  108
- Eight-Way System Interleave of Four 128-Mbyte Memory Modules
  109
  - Refresh
    110
  - Transactions
    110
  - ECC Protection
    110
  - Self-Test
    110
  - Self-Test Modes
    111
  - Self-Test Error Reporting
    112
  - Self-Test Operation
    112
- Self-Test Error Registers
  112
  - Self-Test Performance
    113
- Self-Test Times: Normal Mode
  113
- Self-Test Times: Moving Inversion, no Errors Found
  114
Chapter 5 Memory Interface

115
- Control Address Interface
  115
- TLSB Control
  115
- Memory Bank State Machine
  116
- CSR State Machine
  116
- TLSB Input Latches
  116
- TLSB Bus Monitor
  116
- TLSB Command Decode
  116
- TLSB Bank Match Logic
  117
- TLSB Parity Check
  117
- TLSB Sequence Control
  117
- TLSB Bank Available Flags
  118
- DRAM Control
  118
- Address/Ras Decode Logic
  119
- 128MB/512MB Memory Module Addressing
  119
- 256MB/1024MB Memory Module Addressing
  120
- Two Strings-128MB/512MB Row/Column Address Bit Swapping
  120
  - 512MB/2048MB Memory Module Addressing
    121
- Four Strings-256MB/1024MB Row/Column Address Bit Swapping
  121
- Eight Strings-512MB/2048MB Row/Column Address Bit Swapping
  122
  - Memory Data Interface
    123
  - Data Path Logic
    123
  - Write Data Input Logic
    123
  - Write Data Buffer
    123
  - Write Data Path ECC Algorithm
    123
  - CSR Write Data ECC Check
    124
  - Forcing Write Errors for Diagnostics
    124
  - Write Data out Selection
    125
  - Read Data Output Logic
    125
  - Read Data Buffers
    125
  - Read Data Path ECC Algorithm
    125
  - CSR Read Data ECC
    125
  - MDI Error Detection and Correction Logic
    126
- Error Conditions Monitored by the Mdis
  126
  - CSR Interface
    127
  - CTL CSR Functions
    127
  - TLSB CSR Control
    128
- CSRCA Encoding
  128
  - MAI CSR Sequencer
    129
  - CSR Multiplexing
    130
  - CSRCA Parity
    130
  - MDI CSR Functions
    130
  - MDI CSR Sequencer
    130
  - Merge Register
    131
  - CSR Multiplexing
    131
- CSRCA Data Bus Master
  131
  - CSRCA Parity
    132
Chapter 6 I/O Port

133
- I/O Subsystem Block Diagram
  133
- Configuration
  134
- I/O Port Main Components
  134
- I/O Port Transactions
  135
- Mailbox Transactions
  137
- I/O Window Space Transactions
  139
- CSR Write Transactions to I/O Window Space
  139
- CSR Read Transactions to I/O Window Space
  140
- Interrupt Transactions
  140
- Remote Bus Interrupts
  140
- I/O Port Generated Error Interrupts
  141
- DMA Read Transactions
  142
- DMA Interlock Read Transactions
  142
- DMA Write Transactions
  143
- DMA Unmasked Write
  144
- DMA Masked Write Request to Memory
  144
- Extended NVRAM Write Transactions
  145
- Addressing
  146
- Accessing Remote I/O Node Csrs through Mailboxes
  146
- Accessing Remote I/O Node Csrs through Direct I/O Window Space
  147
- Sparse Address Space Reads
  147
- Sparse Address Space Reads
  148
- Sparse Window Read Data as Presented on the TLSB
  148
  - Sparse Address Space Writes
    149
- Sparse Address Space Read Field Descriptions
  149
- Sparse Address Space Writes
  150
- Sparse Address Space Write Data
  150
- Sparse Address Space Write Field Descriptions
  151
  - Dense Address Space Transactions
    152
- Sparse Address Write Length Encoding
  152
- Dense Address Space Transaction Field Descriptions
  153
- Dense Address Space Write Data
  154
- Dense Window Read Data as Presented on the TLSB
  154
  - TLSB Interface
    155
  - Transactions
    155
  - DMA Transactions
    156
- Transaction Types Supported by the I/O Port
  156
- Wrapped Reads
  157
  - Interrupt Transactions
    158
- I/O Adapter to Memory Write Types
  158
- Write CSR (Interrupt) Data Format
  159
  - CSR Transactions
    160
  - TLSB Arbitration
    162
  - Node 8 I/O Port Arbitration Mode Selection
    163
- Minimum Latency Mode
  164
- Minimum Latency Mode Timing Example
  164
  - Read-Modify-Write
    165
- Toggle 50% High/50% Low Mode
  165
  - Bank Collision Effect on Priority
    166
  - Look-Back-Two
    166
  - Arbitration Suppress
    166
- Error Detection Schemes
  166
- Hose Interface
  167
- Hose Protocol
  167
- Window Space Mapping
  168
- Sparse Address Mapping
  169
- Dense Address Mapping
  169
- Hose Signals
  169
- Down Hose Signals
  170
- Up Hose Signals
  170
- Hose Packet Specifications
  171
- Down Hose Packet Specifications
  171
- Hose Status Signals
  172
- Down Hose Packet Type Codes
  172
- Mailbox Command Packet
  173
- DMA Read Data Return Packet
  174
- Mailbox Command Packet Description
  174
- DMA Read Data Return Packet Description
  175
- DMA Read Data Return Packet with Error
  176
- DMA Read Data Return Packet with Error Description
  176
- INTR/IDENT Status Return Packet
  177
- Sparse Window Read Command Packet
  177
- INTR/IDENT Status Return Packet Description
  177
- Sparse Window Read Command Packet Description
  178
- Sparse Window Write Command Packet
  179
- Dense Window Read Command Packet
  180
- Sparse Window Write Command Packet Description
  180
- Dense Window Read Command Packet Description
  181
- Dense Window Write Command Packet
  182
- Byte Mask Field
  183
- Dense Window Write Command Packet Description
  183
- Up Hose Packet Specifications
  184
- Mailbox Status Return Packet
  185
- Memory Channel Write Packet Description
  185
- DMA Read Packet
  186
- Mailbox Status Return Packet Description
  186
- DMA Read Packet Description
  187
- DMA Read Packet Sizes
  187
- Interlock Read Packet
  188
- Interlock Read Packet Description
  188
- Interlock Read Packet Size
  188
- DMA Masked Write Packet
  189
- DMA Masked Write Packet Description
  190
- DMA Masked Write Packet Sizes
  190
- DMA Unmasked Write Packet
  191
- INTR/IDENT Status Return Packet
  192
- DMA Unmasked Write Packet Description
  192
- Sparse Window Read Data Return Packet
  193
- INTR/IDENT Status Return Packet Description
  193
- Sparse Window Read Data Return Packet Description
  194
- Dense Window Read Data Return Packet
  195
- Dense Window Read Data Return Packet Description
  195
- Window Write Status Return Packet
  196
- Window Write Status Return Packet Description
  196
- Hose Errors
  197
- I/O Port Error Handling
  198
- Soft TLSB Errors Recovered by Hardware
  198
- Hard TLSB Errors
  198
- System Fatal Errors
  198
- Hard Internal I/O Port Errors
  198
- Error Reporting
  199
- Tlsb_Data_Error
  199
- Tlsb_Fault
  200
- IPL 17 Error Interrupts
  201
- Address Bus Errors
  202
- TLSB Address Transmit Check Errors
  202
- Address Bus Parity Errors
  203
- No Acknowledge Errors
  203
- Unexpected Acknowledge
  203
- Bank Busy Violation
  203
- Memory Mapping Register Error
  203
- Data Bus Errors
  204
- Single-Bit ECC Errors
  204
- Double-Bit ECC Errors
  204
- Illegal Sequence Errors
  205
- SEND_DATA Timeout Errors
  205
- Data Status Errors
  205
- Transmit Check Errors
  206
- Multiple Data Bus Errors
  206
- Additional TLSB Status
  206
- Hard I/O Port Errors
  207
- Up Hose Errors
  207
- Up Turbo Vortex Errors
  207
- Down Turbo Vortex Errors
  208
- Miscellaneous I/O Port Errors
  209
- CSR Bus Parity Errors
  209
- Unexpected Mailbox Status Packet
  209
- ICR and IDR Internal Illogical Errors
  209
- Hose Status Change Errors
  210
- KFTIA Overview
  210
- KFTIA Block Diagram
  211
- Integrated I/O Section
  212
- PCI Interface
  213
- Integrated I/O Section of the KFTIA
  213
- SCSI Ports
  214
- Ethernet Ports
  215
- Optional NVRAM Daughter Card
  215
- Integrated I/O Section Transactions
  215
- DMA Transactions
  215
- Mailbox Transaction
  216
- CSR Transactions
  216
- Interrupt Transactions
  216
- PCI 0 and PCI 1 Interrupt Priority
  217
Chapter 7 System Registers

219
- Register Conventions
  219
- Register Address Mapping
  220
- TLSB Node Space Base Addresses
  221
  - TLSB Registers
    222
    
    TLDEV-Device Register
    223
- TLDEV Register Bit Definitions
  223
  - TLBER-Bus Error Register
    225
- TLBER Register Bit Definitions
  226
  - TLCNR-Configuration Register
    232
- TLCNR Register Bit Definitions
  233
  - TLVID-Virtual ID Register
    237
- TLVID Register Bit Definitions
  238
  - Tlmmrn-Memory Mapping Registers
    239
- Tlmmrn Register Bit Definitions
  239
- Interleave Field Values for Two-Bank Memory Modules
  240
- Address Ranges Selected by ADRMASK Field Values
  241
  - Tlfadrn-Failing Address Registers
    242
- Tlfadrn Register Bit Definitions
  242
  - Tlesrn-Error Syndrome Registers
    244
- Tlesrn Register Bit Definitions
  244
  - Tlilidn-Interrupt Level IDENT Registers
    248
- Tlilidn Register Bit Definitions
  248
  - TLCPUMASK-CPU Interrupt Mask Register
    249
- TLCPUMASK Register Bit Definitions
  249
  - TLMBPR-Mailbox Pointer Registers
    250
- TLMBPR Register Bit Definitions
  250
- Mailbox Data Structure Description
  251
  - TLIPINTR-Interprocessor Interrupt Register
    253
- TLIPINTR Register Bit Definitions
  253
  - Tliointrn-I/O Interrupt Registers
    254
- TLI/OINTR Register Bit Definitions
  254
- TLRDRD Register Bit Definitions
  259
  - TLRDRE-CSR Read Data Return Error Register
    260
  - TLMCR-Memory Control Register
    261
- TLMCR Register Bit Definitions
  261
  - CPU Module Registers
    262
- CPU Module Registers
  263
- Gbus Registers
  264
  - TLDIAG-Diagnostic Setup Register
    265
- TLDIAG Register Bit Definitions
  265
  - TLDTAGDATA-Dtag Data Register
    268
- TLDTAGDATA Register Bit Definitions
  268
  - TLDTAGSTAT-Dtag Status Register
    269
- TLDTAGSTAT Register Bit Definitions
  269
  - TLMODCONFIG-CPU Module Configuration Register
    270
- TLMODCONFIG Register Bit Definitions
  270
  - TLEPAERR- ADG Error Register
    272
- TLEPAERR Register Bit Definitions
  273
  - TLEPDERR-DIGA Error Register
    275
- TLEPDERR Register Bit Definitions
  276
  - TLEPMERR-MMG Error Register
    277
- TLEPMERR Register Bit Definitions
  278
  - TLEP_VMG-Voltage Margining Register
    280
- TLEP_VMG Register Bit Definitions
  280
  - TLINTRMASK0-1-Interrupt Mask Registers
    281
- TLEPDERR Register Bit Definitions
  282
  - TLINTRSUM0-1-Interrupt Source Registers
    283
- TLINTRSUM Register Bit Definitions
  284
- Memory Channel Range Register Bit Definitions
  289
  - TLDMCMD-Data Mover Command Register
    290
- TLDMCMD Register Bit Definitions
  291
  - TLDMADRA-Data Mover Source Address Register
    293
- TLDMADRA Register Bit Definitions
  293
  - TLDMADRB-Data Mover Destination Address Reg
    294
- TLDMADRB Register Bit Definitions
  294
  - Gbus$Whami
    295
- GBUS$WHAMI Register Bit Definitions
  295
  - Gbus$Led0,1,2
    296
  - Gbus$Miscr
    297
- GBUS$MISCR Register Bit Definitions
  298
  - Gbus$Miscw
    299
- GBUS$MISCW Register Bit Definitions
  299
  - Gbus$Tlsbrst
    300
  - Gbus$Sernum
    301
- GBUS$SERNUM Register Bit Definitions
  301
  - Memory-Specific Registers
    303
    
    SECR-Serial EEPROM Control/Data Register
    304
- SECR Register Bit Definitions
  304
  - MIR-Memory Interleave Register
    305
- MIR Register Bit Definitions
  306
  - MCR-Memory Configuration Register
    307
- MCR Register Bit Definitions
  308
  - STAIR-Self-Test Address Isolation Register
    311
- STAIR Register Bit Definitions
  311
- STAIR Register Bit Correspondence of Memory Address Segments
  312
  - STER-Self-Test Error Register
    313
- STER Register Bit Definitions
  314
  - MER-Memory Error Register
    315
- MER Register Bit Definitions
  315
  - MDRA-Memory Diagnostic Register a
    316
- MDRA Register Bit Definitions
  316
  - MDRB-Memory Diagnostic Register B
    320
- MDRB Register Bit Definitions
  320
  - STDERA,B,C,D,E-Self-Test Data Error Registers
    321
- STDER A, B, C, D Register Bit Definitions
  322
- STDERE Register Bit Definitions
  323
  - DDR0:3-Data Diagnostic Registers
    324
- Ddrn Register Bit Definitions
  324
  - I/O Port-Specific Registers
    327
- I/O Port-Specifc Registers
  327
  - RMRR0-1-Memory Channel Range Registers
    328
- RMRR0-1 Register Bit Definitions
  329
  - ICCMSR-I/O Control Chip Mode Select Register
    330
- ICCMSR Register Bit Definitions
  330
  - ICCNSE-I/O Control Chip Node-Specific Error Reg
    335
- ICCNSE Register Bit Definitions
  336
  - ICCDR-I/O Control Chip Diagnostic Register
    340
- ICCDR Register Bit Definitions
  341
  - ICCMTR-I/O Control Chip Mailbox Transaction Reg
    343
- ICCMTR Register Bit Definitions
  344
  - ICCWTR-I/O Control Chip Window Transaction Reg
    345
- ICCWTR Register Bit Definitions
  345
  - IDPNSE0-3-I/O Data Path Node-Specific Error Regs
    346
- IDPNSE0-3 Register Bit Definitions
  347
  - Idpdrn-I/O Data Path Diagnostic Registers
    351
- IDPDR0-3 Register Bit Definitions
  352
- Error Matrix for Force Error Bits
  354
  - IDPVR-I/O Data Path Vector Register
    355
- IDPVR Register Bit Definitions
  355
  - IDPMSR-I/O Data Path Mode Select Register
    356
- IDPMSR Register Bit Definitions
  357
  - IBR-Information Base Repair Register
    358
- IBR Register Bit Definitions
  359
  - KFTIA Specific Registers
    360
Chapter 8 Interrupts

361
- Vectored Interrupts
  361
- I/O Port Interrupt Rules
  361
- CPU Interrupt Rules
  362
- I/O Port Interrupt Operation
  362
- Nonvectored Interrupts
  363
- I/O Interrupt Mechanism
  363
- TLSB Principles for Interrupts
  363
- Virtual Node Identification - TLVID
  364
- Directing Interrupts - TLCPUMASK
  364
- Directing Interrupts - TLINTRMASK
  364
- Interrupt Registers - TLIOINTR4-8
  364
- Generating Interrupts
  365
- Servicing Interrupts
  365
  - Interprocessor Interrupts
    365
- Module-Level Interrupts
  366
- CPU Module Interrupts
  366

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