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ting <UECC>. A UECC error causes the I/O port to set TLBER<UDE>
and assert TLSB_DATA_ERROR. An IPL 17 is also posted, if enabled by
software.
If the error was detected on data that the I/O port was writing to memory,
then TLESR<TDE> and TLBER<DTDE> bits are also set.
If the error is detected on a read type instruction, a down Turbo Vortex
read return data packet is sent to the HDR. However, each IDR that de-
tected an error asserts the down Turbo Vortex RER signal to the HDR for
the duration of the packet. The down HDR detects the assertion of the
RER signal and creates a one cycle DMA read data with error packet to be
sent down the target hose. The assertion of RER on the down Turbo Vor-
tex is valid for any DMA read data packets, whether they result from a
DMA read or a DMA IREAD.
If the uncorrectable error is detected on read lock data, the failing
quadword(s) are tagged as bad when loaded into the Memory Channel
buffers in the IDRs. The I/O port issues the Write Unlock command to
free the memory bank. However, because the integrity of the data has
been lost, the data cannot be written back to memory. Each IDR on the
I/O port has the capability of not driving (that is, defaulting) the TLSB
data bus, in the event that the data had been tagged as bad. Note that
while this action does result in a second uncorrectable ECC error being de-
tected, it has the desirable feature of unlocking the memory bank.
6.7.8.3
Illegal Sequence Errors
An illegal sequence error occurs when the bus sequence value that is trans-
mitted with TLSB_SEND_DATA is different from the expected sequence
number. The I/O port sets TLBER<SEQE> and asserts the TLSB_FAULT
signal. The I/O port also detects an illegal sequence error if TLSB_SEND_
DATA is received and there was no outstanding TLSB command.
6.7.8.4
SEND_DATA Timeout Errors
The I/O port begins a timeout count when a data bus sequence slot is
reached and the I/O port is expecting a slave to return data. If the I/O port
does not receive TLSB_SEND_DATA for 256 cycles, it logs a DTO error in
its TLBER register and asserts TLSB_FAULT. Note that if TLSB_HOLD
is asserted during this transaction, the timeout counter is not incremented.
As a result the timeout count is effectively extended by the number of Hold
cycles (that is, the timeout count equals 256 plus the number of Hold cy-
cles).
6.7.8.5
Data Status Errors
The TLSB_STATCHK signal is used as a check on the logical OR of
TLSB_SHARED and TLSB_DIRTY. Two cycles after TLSB_SEND_DATA
is seen on the TLSB, and every two cycles thereafter if TLSB_HOLD is as-
serted, the I/O port checks these signals. If, during this check, the I/O port
receives either TLSB_SHARED or TLSB_DIRTY asserted while TLSB_
STATCHK is deasserted, or if TLSB_STATCHK is asserted while TLSB_
SHARED and TLSB_DIRTY are both deasserted, the I/O port sets its TL-
BER<DSE> and asserts TLSB_FAULT.
I/O Port 6-73
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