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Table 7-57 ICCDR Register Bit Definitions (Continued)
Name
DIS_TLSB_FAULT
DIS_TLSB_CMD
FRC_DTO
FRC_DSE
FRC_IDR_CSR_BUS
_PE
7-124 System Registers
Bit(s)
Type
Function
<4>
R/W, 0
Disable TLSB Fault. Setting this bit prevents
the I/O port from driving TLSB_FAULT even if a
system fatal error condition is detected by the
I/O port. It allows diagnostics to force various
fatal TLSB errors (such as APE, ATCE, BBE,
DTO, DSE) and various fatal Up Turbo Vortex
errors without crashing the system.
NOTE: Disabling the I/O port from driving
TLSB_FAULT may prevent the I/O port from re-
covering (for example, resyncing gate arrays and
TLSB) after a fatal error condition is detected,
and may require a node reset.
<3>
R/W, 0
Disable TLSB Command Transmission.
This feature prevents the I/O port from trans-
mitting Up Turbo Vortex packets onto the TLSB.
It does not prevent the I/O port from responding
to CSR reads/writes or from fetching mailbox
structures from TLSB memory and sending a
Mailbox Command packet on the Down Hose.
Once the bit is cleared, the I/O port processes all
the transactions in its Up Turbo Vortex buffers.
<2>
R/W, 0
Force Data Timeout Error. Inhibits sending
data after starting a broadcast write command
on the TLSB.
<1>
W, 0
Force Data Status Error. Flips the signal
TLSB_STATCHK during a TLSB transaction. It
clears automatically after one transaction.
<0>
R/W, 0
Force IDR CSR Bus Parity Error. When set,
the ICR forces bad parity on the CSR data bus
to IDR0 whenever a register in the ICR is read.
This causes IDR0 to set IDPNSE0<IDR_ CSR_
BUS_PE>. Forcing this error also sets TLESR0-
<UECC>, TLESR0<TDE>, TLBER<DTDE>, and
TLBER<UDE>.
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