Secr-Serial Eeprom Control/Data Register; Secr Register Bit Definitions - DEC AlphaServer 8200 Technical Manual

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SECR—Serial EEPROM Control/Data Register
Address
BB + 0000 1800
Access
R/W
The SECR register is used to access the EEPROM on the memory
module. Access to the EEPROM is accomplished by continual up-
dates of this register by software.
31
Table 7-41 SECR Register Bit Definitions
Name
Bit(s)
<31:3>
RSVD
<2>
SCLK
<1>
XMT_SDAT
<0>
RCV_SDAT
7-86 System Registers
RSVD
Type
Function
R0
Reserved. Read as zero.
R/W, 0
Serial Clock. Used to implement the EEPROM
serial clock interface by software. When this bit
is written with a one, the EEPROM serial clock
input is forced to a logic high. When this bit is
cleared the serial clock input is forced to low
logic level.
R/W, 1
Transmit Serial Data. Used by software to as-
sert the serial data line of the EEPROM to either
high or low logic levels. This bit is used with the
SCLK bit to transfer command, address, and
write data to the EEPROM. Must be set to one
to receive an EEPROM response or serial read
data.
R
Receive Serial Data. Returns the status of the
EEPROM serial data line. This bit is used by
software to receive serial read data and
EEPROM responses.
4
3
2
1
0
SCLK
XMT_SDAT
RCV_SDAT
BXB-0729-94

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