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3.4 CPU Module Window Space Support
CSRs that exist on some external I/O buses are accessed through window
space transactions. Rather than issuing a read command and waiting for
data to be returned to the CPU module from an external I/O bus, the CPU
module and I/O port have a protocol to permit disconnected reads. This al-
lows a CPU module to access external I/O CSRs without holding the bus
for long periods of time.
To read or write a window space location, a CPU issues a read or write
command to a CSR space address.
3.4.1 Window Space Reads
When a CPU module issues a CSR read to window space, a CPU module
asserts the VID (virtual ID) value of the CPU involved in the transfer onto
the TLSB_BANK_NUM lines. The targeted I/O port latches the address
and the VID value. The I/O port cycles the data bus as if it were returning
data (the data returned at this stage is Unpredictable), allowing the data
bus to proceed. The CPU module ignores this returned data and waits for
a write to the CSR Read Data Return Data Register by the I/O port.
Upon receipt of a CSR read command to window space, the I/O port creates
a window read command packet and sends this down a hose to an external
I/O bus. Sometime later, when data is returned to the I/O port up the
hose, the I/O port issues a CSR write to the CSR Read Data Return Data
Register (BSB+800). The I/O port asserts the VID of the initiating CPU on
the TLSB_BANK_NUM lines. The write data associated with this CSR
write is the fill data that the CPU module requested. The CPU module
recognizes its data return packet based on the VID issued by the I/O port.
It then accepts the data as though it were CSR read data and completes
the fill to the CPU.
3.4.2 Window Space Writes
CSR writes to window space function like nonwindow space CSR reads.
Each time the DECchip 21164 issues a CSR write, it transfers 32 bytes ac-
companied by INT4_DATA_VALID bits that indicate which of the eight
longwords have been modified. The CPU module drives the 32 bytes of
data onto the TLSB in the first data cycle of its TLSB data transfer. It
drives the data valid bits in the second data cycle. The I/O port uses these
bits to assemble an appropriate Down Hose packet.
3.4.3 Flow Control
The I/O port has sufficient buffering to store up to four I/O window trans-
actions. Flow control is maintained using the I/O window space queue
counters in the CPU module. Each CPU module increments its associated
I/O queue counter whenever it sees an I/O window space transaction on the
TLSB. When the I/O port empties a window write command packet from
its buffers to the hose (in the event of a write), it issues a CSR write com-
mand to its assigned Window Space Decrement Queue Counter register, as
shown in Table 3-4.
3-10 CPU Module
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