512Mb/2048Mb Memory Module Addressing; Four Strings-256Mb/1024Mb Row/Column Address Bit Swapping - DEC AlphaServer 8200 Technical Manual

Table 5-3 Four Strings—256MB/1024MB Row/Column Address Bit Swapping
DRAM Type
No. of Banks
Interleaved
DRAM Address
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Mod_Sel<0>
Mod_Sel<0>
Mod_Sel<0>
Bank_Sel<0>
Ras_Sel<0>
Ras_Sel<1>
Key to 4M DRAM Unused Row Addresses/Ras_Sel and Mod_Sel:
x(n) : Don't Care. (n) is the address bit driven even though it is not used by the DRAMs.
x : Don't Care. No address bits are involved in this decision.
"0" : Always 0. This signal is always held deasserted.
5.1.3.3

512MB/2048MB Memory Module Addressing

Table 5-4 shows how the TLSB addresses are allocated for an eight-string
memory module. As shown, Ras_Sel<1:0> are now affected by addresses
since we need to select one of the four strings per bank.
4 Mbit
1 2 4
7 7 7
8 8 8
9 9 9
10 10 10
11 11 11
12 12 12
13 13 13
14 14 14
15 15 15
16 16 16
x(21) x(21) x(21)
x(22) x(22) x(22)
21 21 21
22 22 22
3 23 23
4 4 24
5 5 5
6 6 6
17 17 17
18 18 18
19 19 19
20 20 20
x 1 1
x x 2
x x x
1 2 3
2 3 4
"0" "0" "0"
16 Mbit
8 1 2
7 7 7
8 8 8
9 9 9
10 10 10
11 11 11
12 12 12
13 13 13
14 14 14
15 15 15
16 16 16
x(21) 21 21
x(22) 22 22
21 23 23
22 24 24
23 3 25
24 4 4
25 5 5
6 6 6
17 17 17
18 18 18
19 19 19
20 20 20
1 x 1
2 x x
3 x x
4 1 2
5 2 3
"0" "0" "0"
4 8
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
21 21
22 22
23 23
24 24
25 25
26 26
5 27
6 6
17 17
18 18
19 19
20 20
1 1
2 2
x 3
3 4
4 5
"0" "0"
Memory Interface 5-7