DEC AlphaServer 8200 Technical Manual page 5

2.4.3.8 Multiple Address Bus Errors ......................................................................... 2-38
2.4.3.9 Summary of Address Bus Errors .................................................................. 2-38
2.4.4 Data Bus Errors .................................................................................................... 2-39
2.4.4.1 Single-Bit ECC Errors ................................................................................... 2-40
2.4.4.2 Double-Bit ECC Errors .................................................................................. 2-40
2.4.4.3 Illegal Sequence Errors .................................................................................. 2-40
2.4.4.4 SEND_DATA Timeout Errors ....................................................................... 2-40
2.4.4.5 Data Status Errors ......................................................................................... 2-41
2.4.4.6 Transmit Check Errors .................................................................................. 2-41
2.4.4.7 Multiple Data Bus Errors .............................................................................. 2-41
2.4.4.8 Summary of Data Bus Errors ........................................................................ 2-42
2.4.5 Additional Status .................................................................................................. 2-42
2.4.6 Error Recovery ...................................................................................................... 2-43
2.4.6.1 Read Errors .................................................................................................... 2-43
2.4.6.2 Write Errors ................................................................................................... 2-45
Chapter 3 CPU Module
3.1 Major Components ........................................................................................................ 3-1
3.1.1 DECchip 21164 Processor ...................................................................................... 3-2
3.1.2 MMG ...................................................................................................................... 3-3
3.1.3 ADG ........................................................................................................................ 3-3
3.1.4 DIGA ...................................................................................................................... 3-3
3.1.5 B-Cache .................................................................................................................. 3-4
3.2 Console ........................................................................................................................... 3-4
3.2.1 Serial ROM Port ..................................................................................................... 3-5
3.2.2 Directly Addressable Console Hardware .............................................................. 3-5
3.3 CPU Module Address Space ......................................................................................... 3-6
3.3.1 Memory Space ......................................................................................................... 3-7
3.3.2 I/O Space ................................................................................................................. 3-8
3.3.2.1 I/O Window Space ............................................................................................ 3-8
3.3.2.2 TLSB CSR Space ............................................................................................. 3-8
3.3.2.3 Gbus Space ....................................................................................................... 3-9
3.4 CPU Module Window Space Support ......................................................................... 3-10
3.4.1 Window Space Reads ............................................................................................ 3-10
3.4.2 Window Space Writes ........................................................................................... 3-10
3.4.3 Flow Control ......................................................................................................... 3-10
3.4.4 PCI Accesses ......................................................................................................... 3-11
3.4.4.1 Sparse Space Reads and Writes .................................................................... 3-12
3.4.4.2 Dense Space Reads and Writes ..................................................................... 3-13
3.5 CPU Module Errors ................................................................................................... 3-14
3.5.1 Error Categories ................................................................................................... 3-14
3.5.1.1 Soft Errors ...................................................................................................... 3-14
3.5.1.2 Hard Errors .................................................................................................... 3-14
3.5.1.3 Faults .............................................................................................................. 3-15
3.5.1.4 Nonacknowledged CSR Reads ....................................................................... 3-16
3.5.2 Address Bus Errors ............................................................................................. 3-16
3.5.2.1 Transmit Check Errors .................................................................................. 3-17
3.5.2.2 Command Field Parity Errors ....................................................................... 3-17
3.5.2.3 No Acknowledge Errors ................................................................................. 3-18
3.5.2.4 Unexpected Acknowledge Error .................................................................... 3-18
3.5.2.5 Memory Mapping Register Error .................................................................. 3-18
3.5.3 Data Bus Errors .................................................................................................... 3-18
3.5.4 Multiple Errors ..................................................................................................... 3-19
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