Dma Unmasked Write; Dma Masked Write Request To Memory - DEC AlphaServer 8200 Technical Manual

requires a single TLSB bus write transaction and is always a double
hexword.
A DMA write request packet is executed as a disconnected (write-and-run)
operation and therefore has no status return packet associated with it.
Once the I/O bus adapter transmits the DMA write request packet over the
Up Hose, the transaction is complete.
6.3.6.1

DMA Unmasked Write

The DMA unmasked write packet is the most efficient DMA write that the
I/O port supports. It has two major advantages over the DMA masked
write packet. First, it only requires a single write on the TLSB bus,
whereas a DMA masked write packet requires a Read-Modify-Write opera-
tion on the TLSB bus. Second, the data length of a DMA unmasked write
packet is a double hexword in length, whereas a DMA masked write
packet can be as small as a byte of valid data (but will usually match the
size of the DMA write on the I/O bus). On the XMI this will probably
equate to octaword writes. If so, it would require four Read-Modify-Write
operations on the TLSB bus to match just one unmasked double hexword
write. The DMA write performance increases dramatically whenever a
DMA unmasked write packet is used in place of a DMA masked write
packet.
Generally speaking, an I/O adapter module should be able to utilize the
speed of a DMA unmasked write packet by using a protocol that appends
the smaller size writes on the I/O bus into a double hexword and shipping
them across the Up Hose as a DMA unmasked write packet. The XMI I/O
module uses the XMI MORE protocol to accomplish this task.
The DMA unmasked write packet includes the TLSB target address for the
data and a double hexword of write data.
After receiving the DMA unmasked write packet, the I/O port executes the
write to memory over the TLSB bus. If no errors are detected, the DMA
write transaction is complete. If an error is detected on the Up Hose (for
example, a parity error or sequence error), or if the TLSB bus write is un-
successful, the I/O port logs the error and generates an error interrupt to
the CPU(s).
6.3.6.2

DMA Masked Write Request to Memory

The DMA masked write packet includes the target address for the data,
the length code to allow for sequence checking, mask bits in the UPCTL
field, and the amount of data required for the DMA masked write.
After receiving the DMA masked write packet, the I/O port executes a
Read Bank Lock to TLSB memory at the target address. This causes the
TLSB memory to deassert and hold its TLSB_BANK_AVL signal until it
receives a Write Bank Unlock command. When the data is returned from
TLSB memory, the I/O port merges the DMA write data (using the mask
bits from the DMA write packet) and writes it back to memory using a
Write Bank Unlock command. If this I/O port is node 8, the data is written
back immediately using the highest priority arbitration ID (TLSB_REQ8_
HIGH) to minimize latency. If the I/O port is not node 8, the I/O port uses
TLSB_REQn, where n is the node number. Atomicity is guaranteed by the
Read Bank Lock/Write Bank Unlock TLSB commands. If no errors were
detected, the DMA masked write transaction is complete. If an error is
6-12 I/O Port