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6.7.8.6
Transmit Check Errors
The I/O port level checks the TLSB_D<255:0> and TLSB_ECC<31:0>
fields when it is driving data on the TLSB bus. The I/O port sets <TCE> in
its TLESRn register if it detects a mismatch. Since ECC is checked on the
data received from the bus, a TCE error usually causes the I/O port to set
one of <UECC>, <CWECC>, or <CRECC>. If <TCE> should set without
any other error bit, a case where other nodes will receive this data and
think it is good, the I/O port sets <FDTCE> in its TLBER register and as-
serts TLSB_FAULT.
The I/O port level checks TLSB_SEQ<3:0> whenever it asserts
TLSB_SEND_DATA. If it detects a mismatch, it sets <DCTCE> and as-
serts TLSB_FAULT.
The I/O port assertion checks TLSB_SEND_DATA only when it is being
asserted by the I/O port. If the I/O port detects a mismatch, it sets <DC-
TCE> in its TLBER register and asserts TLSB_FAULT.
The I/O port assertion checks TLSB_HOLD only when it is being asserted
by the I/O port. If the I/O port detects a mismatch, it sets <DCTCE> in its
TLBER register and asserts TLSB_FAULT.
The I/O port assertion checks TLSB_DATA_ERROR only when it is being
asserted by the I/O port. If the I/O port detects a mismatch, it sets <DC-
TCE> in its TLBER register and asserts TLSB_FAULT.
The I/O port level checks TLSB_DATA_VALID when it is driving data on
the TLSB. If it detects a mismatch, it sets <DVTCE>, which results in
<CRDE> or <CWDE> (depending on the TLSB command) being set in its
TLBER register. This causes the I/O port to issue an IPL 17 interrupt if
interrupts are enabled.
NOTE: TLSB_SHARED, TLSB_DIRTY, and TLSB_STATCHK are never asserted
by the I/O port; therefore, no transmit checking for these signals is imple-
mented on the I/O port.
6.7.8.7
Multiple Data Bus Errors
Hard and soft data bus errors are cumulative. Should a second error con-
dition occur, the I/O port asserts TLSB_DATA_ERROR a second time. If
the error is of a different type than the first, the I/O port sets an additional
error bit in its TLBER register.
System fatal data bus errors are cumulative. Should a second system fatal
error condition occur, the I/O port asserts TLSB_FAULT a second time. If
a fatal error is of a different type than the first, the I/O port sets an addi-
tional error bit in its TLBER register.
6.7.9 Additional TLSB Status
In addition to the error bits in the TLBER and TLESRn registers, the I/O
port preserves additional status on detection of errors.
6-74 I/O Port
• The TLESRn registers contain syndrome fields that are latched on the
detection of ECC errors with the failing syndrome.
• The TLBER register (<DS0-3>) records which TLESRn register con-
tains error status corresponding to the most significant error condition
detected for which additional error status has been saved.
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