I/O Architecture - DEC AlphaServer 8200 Technical Manual

ported by a single motherboard design. The 2-Gbyte memory option uses
a different motherboard and SIMM design.
A maximum of seven memory modules may be configured on the TLSB (in
a system with one CPU module and one I/O module). Thus, the maximum
memory size is 14 Gbytes, using 2-Gbyte modules.
Memory operates within the 10–30 ns TLSB cycle time range. To keep
memory latency low, the memory module supports three different DRAM
cycle times. As TLSB cycle time is decreased (slowed down), the memory
module cycle time can be increased (sped up) to ensure that data latency
remains relatively constant, independent of TLSB cycle time.
Each memory module is organized into two banks of independently accessi-
ble random memory. Bank interleaving occurs on 64-byte boundaries,
which is the TLSB data transfer size.
Different size memory modules can be interleaved together. For example,
four 128-Mbyte modules can be combined to appear as a single 512-Mbyte
module, and this set can be interleaved with a 512-Mbyte module. In this
case, the five modules are four-way interleaved.
Memory is protected by a 64-bit ECC algorithm. An 8-bit ECC check code
protects each 64 bits of data. This algorithm allows correction of single-bit
failures and the detection of double-bit and some nibble failures. The same
algorithm is used to protect data across the TLSB and within the CPU
module caches. ECC is checked by the memory when data is read out of
memory. It is also checked when data is received from the TLSB, prior to
writing data into the memory. Memory is designed so that a single failing
DRAM cannot cause an uncorrectable memory error.
The memory module does not correct ECC errors. If a data block contain-
ing a single-bit ECC error is written by a CPU or I/O device to memory, the
memory checks the ECC and signals a correctable error, but it does not
correct the data. The data is written to the DRAMs with the bad ECC
code. Only CPU and I/O port modules correct single-bit ECC errors.
Refer to Chapters 4 and 5 for a thorough discussion of the memory module.

1.5 I/O Architecture

The I/O system components consist of:
The KFTHA and KFTIA modules reside on the TLSB and provide the in-
terface between the TLSB and optional I/O subsystems.
The KFTHA provides connections for up to four optional XMI, Futurebus+,
or PCI buses, in any combination, through a cable called a hose.
The KFTIA provides a connection to one optional XMI, Futurebus+, or PCI
bus through a hose. It also contains an on-module PCI bus with connec-
• I/O port module (KFTHA)
• Integrated I/O port module (KFTIA)
• XMI bus adapter (DWLMA)
• Futurebus+ adapter (DWLAA)
• PCI bus adapter (DWLPA)
• Memory Channel interface (RM in register mnemonics)
Overview 1-5