I/O Port-Specific Registers; I/O Port-Specifc Registers - DEC AlphaServer 8200 Technical Manual

7.6 I/O Port-Specific Registers

The I/O port responds to all addresses within its node space. If, however,
the I/O port receives a read to a nonimplemented CSR, the I/O port returns
Unpredictable data, with good ECC. Table 7-53 shows the mapping of the
I/O port-specific registers.
Table 7-53 I/O Port-Specifc Registers
Mnemonic Name
Memory Channel Range Register 0A
RMRR0A
Memory Channel Range Register 1A
RMRR1A
Memory Channel Range Register 0B
RMRR0B
RMRR1B Memory Channel Range Register 1B
I/O Control Chip Mode Select Register
ICCMSR
I/O Control Chip Node-Specific Error Register
ICCNSE
I/O Control Chip Diagnostic Register
ICCDR
I/O Control Chip Mailbox Transaction Register
ICCMTR
ICCWTR I/O Control Chip Window Transaction Register
I/O Data Path Node-Specific Error Register 1
IDPNSE1
I/O Data Path Diagnostic Register 1
IDPDR1
I/O Data Path Node-Specific Error Register 2
IDPNSE2
I/O Data Path Diagnostic Register 2
IDPDR2
I/O Data Path Node-Specific Error Register 3
IDPNSE3
IDPDR3 I/O Data-Path Diagnostic Register 3
I/O Data Path Node-Specific Error Register 0
IDPNSE0
I/O Data Path Diagnostic Register 0
IDPDR0
IPCPU Mask Register
IPCPUMR
I/O Data Path Vector Register
IDPVR
IDPMSR I/O Data Path Mode Select Register
Information Base Repair Register
IBR
Down Hose Range Register 0A
DHR0A
Down Hose Range Register 1A
DHR1A
Down Hose Range Register 0B
DHR0B
Down Hose Range Register 1B
DHR1B
Address
BB+1E00
BB+1E40
BB+1E80
BB+1EC0
BB+2000
BB+2040
BB+2080
BB+20C0
BB+2100
BB+2140
BB+2180
BB+2240
BB+2280
BB+2340
BB+2380
BB+2A40
BB+2A80
BB+2AC0
BB+2B40
BB+2B80
BB+2BC0
BB+3000
BB+3040
BB+3080
BB+30C0
System Registers 7-109