module can result in reduced system throughput due to common data path
contention between the two banks.
At the module level, the DRAM arrays can be interleaved on 64-byte block
boundaries. The DRAM array in a 2-string MS7CC memory module is al-
ways interleaved.
In multimodule memory subsystems, three modes of interleave are possi-
ble at the system level: default, explicit, and none. The interleave mode
selection parameters are stored in the console FEPROM and can be modi-
fied through the console program. Initialization software uses registers in
TLSB commanders and each memory module to configure the memory in-
terleave as specified by the FEPROM parameters. A memory configura-
tion consisting of four memory modules supports a maximum of 8-way in-
terleaving when each of the four modules is 2-way interleaved. The three
additional modules (modules 5 to 7), if present, can be configured into the
system as two modules 4-way interleaved and 1 module 2-way interleaved.
Figure 4-7 shows four memory modules in an 8-way interleaved organiza-
tion.
Figure 4-7
Eight-Way System Interleave of Four 128-Mbyte Memory Modules
2-Way Module Interleave; No System Interleave
Bank 0
0000 0000 0000 0040
0000 0080 0000 00C0
07FF FF80 07FF FFC0
2-Way Module Interleave; 8-Way System Interleave
Bank 0
1
0000 0000 0000 0100
0000 0200 0000 02FF
1FFF FE00 1FFF FF00
Block size
= 64 Bytes
DRAM size
=
Memory Capacity = 512 Mbytes
If the FEPROM specifies default interleave, the console attempts to form
interleave sets so that the largest interleave factor is obtained for each
1
2
3
0800 0000 0800 0040
0800 0080 0800 00C0
0FFF FF80 0FFF FFC0
2
3
0000 0040 0000 0140
0000 0240 0000 033F
1FFF FE40 1FFF FF40
4 Mbits
4
5
1000 0000 1000 0040
1800 0000 1800 0040
1000 0080 1000 00C0
1800 0080 1800 00C0
17FF FF80 17FF FFCO
IFFF FF80 IFFF FFC0
4
5
0000 0080 0000 0180
0000 00C0 0000 01C0
0000 0280 0000 037F
0000 02C0 0000 03BF
1FFF FE80 1FFF FF80
1FFF FEC0 1FFF FFC0
Memory Subsystem 4-15
6
7
6
7
BXB-0307-92