Idpdr0-3 Register Bit Definitions - DEC AlphaServer 8200 Technical Manual

Table 7-61 IDPDR0–3 Register Bit Definitions
Name
VOLT_MARG
DIS_DN_HOSE_RST
RSVD
FRC_EOP_SEQ_ERR
7-134 System Registers
Bit(s) Type Function
<31> R/W, 0 Voltage Margin. When set, the module's 5.0
and 3.35 volt DC to DC converters are margined
over a +/− 5% range.
NOTE: If both plus and minus margining bits
are set for a given voltage, the DC to DC con-
verter goes to its nominal output voltage.
The VOLT_MARG bit is not cleared by a node
reset. It is only cleared at system power-up.
<30> R/W, 0 Disable Down Hose Reset. When set, pre-
vents DHRST L from asserting during an I/O
port node reset. This allows diagnostics to reset
the I/O port without resetting the entire I/O
subsystem. Each IDPDR register corresponds
to a particular hose as follows:
<29:21> R/W, 0 Reserved. Read as zeros.
<20> R/W, 0 Force Down EOP Sequence Error. When
set, forces an early assertion of down Turbo Vor-
tex EOP for down Turbo Vortex Mailbox Com-
mand packets.
IDR Register Voltage
IDPDR0 5.0
5.0
IDPDR1
3.5.
IDPDR2
3.5
IDPDR3
IDR Register Affected Hose
IDPDR0
IDPDR1
IDPDR2
IDPDR3
Margin
+5%
−5%
+5%
−5%
0
1
2
3