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Figure 4-3
Cache Index and Tag Mapping to Block Address (16MB)
4.2.3 Updates and Invalidates
If a block is shared, and a CPU wants to write it, the write must be issued
on the TLSB. Writes of a shared block cause the block to be invalidated in
the cache of all CPUs other than the one that issued the write.
4.2.4 Duplicate Tags
To determine whether a block is resident in a CPU's cache, each TLSB ad-
dress must be compared against the tag address of the block at that ad-
dress. Checking the address in the B-cache tag stores would be inefficient
as it would interfere with DECchip 21164 access to the B-cache. To facili-
tate the check without penalizing DECchip 21164 cache access, a duplicate
tag store, called the DTag, is maintained.
The DTag contains copies of both tag stores on the module. Lookups in the
DTag are done over two successive cycles, the first for CPU0, the second
for CPU1. The results of the two lookups can be different (and in general
will be) as the two B-caches are totally independent.
4.2.5 B-Cache States
The B-cache state is defined by the three status bits: Valid, Shared, and
Dirty. Table 4-1 shows the legal combinations of the status bits.
From the perspective of the DECchip 21164, a tag probe for a read is suc-
cessful if the tag matches the address and the V bit is set. A tag probe for
a write is successful if the tag matches the address, the V bit is set, and
the S bit is clear.
4-4 Memory Subsystem
39
38
Processor Byte Address
0
38
Tag<38:24>
24
23
B-Cache Index<23:6>
Wrap Order
BXB0822.AI
6
5
4
6
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