DEC AlphaServer 8200 Technical Manual page 255

means that all CPUs accept writes to these registers. Multiple writes to a
register post multiple interrupts. Reads to these locations produce Unpre-
dictable results.
A CPU receiving one of the four bits set in its target assignment is ex-
pected to respond by reading a TLILIDn register in the I/O node and dis-
patch an interrupt based on the IDENT vector. The four bits determine
the specific TLILIDn register to be read as follows:
• TLILID0 is read if <IPL 14 INTR> is set
• TLILID1 is read if <IPL 15 INTR> is set
• TLILID2 is read if <IPL 16 INTR> is set
• TLILID3 is read if <IPL 17 INTR> is set
System Registers 7-37