Dram Arrays - DEC AlphaServer 8200 Technical Manual

DRAM arrays. The MDI includes data buffers, ECC checking logic, self-
test data generation and checking logic, and CSRs.
MDI concatenates two 72-bit TLSB transfers into one 144-bit transfer to
the DRAMs during memory writes. During memory reads, 144-bit reads
from the DRAMs are issued onto the TLSB via two 72-bit consecutive
transfers.
During memory writes, each MDI contains two 144-bit write data buffers
that are used to:
During memory reads, each MDI contains a read buffer for DRAM bank0
and DRAM bank1. Each read buffer can store 144 bits of read data. The
read buffer performs several functions:
MDI contains the ECC checking logic that is used to check memory write
data and memory read data to aid in system fault isolation. The ECC
check bits are slightly modified before that data is written into the DRAMs
by the addition of a Row and a Col parity bit. The purpose is to boost sys-
tem data integrity in case of a single-bit Row or Col address failure. Dur-
ing memory reads, the modified ECC check bits are stripped of the
Row/Col parity bits before data and check bits are driven onto the TLSB.
4.3.1.3

DRAM Arrays

The DRAM arrays consist of DRAMs, control signal, and address buffer
components. The MS7CC memory modules can use DRAM sizes of 1M x 4
bits or 4M x 4 bits. The DRAM arrays are organized into 2 to 8 strings.
Each string requires 144 DRAMs (using DRAMs with quadword ECC), re-
gardless of the DRAM type. The DRAM array on each memory module is
configured with two independently accessible banks. To support two
banks, a minimum of two strings (128 Mbytes) is required.
Interleaving of DRAM banks increases memory bandwith. Each memory
module supports 2-way interleaving when configured with a minimum of
two strings. Interleaving occurs between the two independently accessible
banks within a module. A memory configuration on the TLSB consisting of
4-12 Memory Subsystem
• Temporarily store the first data cycle (72 bits) from the TLSB until the
second arrives and the write can be completed.
• Store all 144 bits, so that write data can be accepted off the TLSB inde-
pendent of refresh or read operations to the other bank which may re-
sult in delaying the completion of the write from the memory's perspec-
tive.
• Unwrap wrapped write transactions before write data is written to the
DRAM array.
• Temporarily stores the second TLSB data cycle, while the first is being
output onto the TLSB bus.
• Stores either one or two banks worth of read data, which is necessary if
TLSB_HOLD is asserted, or if TLSB is very busy. Once RAS is as-
serted, the transaction MUST be completed.
• Wraps read data when TLSB_ADR<5> is asserted on the TLSB during
a memory read command/address cycle.
• Contains "data-muxing" used to select between memory "fast-path"
data, read buffer data, or CSR read data.